xref: /linux/include/dt-bindings/clock/stih407-clks.h (revision e0bf6c5ca2d3281f231c5f0c9bf145e9513644de)
1 /*
2  * This header provides constants clk index STMicroelectronics
3  * STiH407 SoC.
4  */
5 #ifndef _DT_BINDINGS_CLK_STIH407
6 #define _DT_BINDINGS_CLK_STIH407
7 
8 /* CLOCKGEN C0 */
9 #define CLK_ICN_GPU		0
10 #define CLK_FDMA		1
11 #define CLK_NAND		2
12 #define CLK_HVA			3
13 #define CLK_PROC_STFE		4
14 #define CLK_PROC_TP		5
15 #define CLK_RX_ICN_DMU		6
16 #define CLK_RX_ICN_DISP_0	6
17 #define CLK_RX_ICN_DISP_1	6
18 #define CLK_RX_ICN_HVA		7
19 #define CLK_RX_ICN_TS		7
20 #define CLK_ICN_CPU		8
21 #define CLK_TX_ICN_DMU		9
22 #define CLK_TX_ICN_HVA		9
23 #define CLK_TX_ICN_TS		9
24 #define CLK_ICN_COMPO		9
25 #define CLK_MMC_0		10
26 #define CLK_MMC_1		11
27 #define CLK_JPEGDEC		12
28 #define CLK_ICN_REG		13
29 #define CLK_TRACE_A9		13
30 #define CLK_PTI_STM		13
31 #define CLK_EXT2F_A9		13
32 #define CLK_IC_BDISP_0		14
33 #define CLK_IC_BDISP_1		15
34 #define CLK_PP_DMU		16
35 #define CLK_VID_DMU		17
36 #define CLK_DSS_LPC		18
37 #define CLK_ST231_AUD_0		19
38 #define CLK_ST231_GP_0		19
39 #define CLK_ST231_GP_1		20
40 #define CLK_ST231_DMU		21
41 #define CLK_ICN_LMI		22
42 #define CLK_TX_ICN_DISP_0	23
43 #define CLK_TX_ICN_DISP_1	23
44 #define CLK_ICN_SBC		24
45 #define CLK_STFE_FRC2		25
46 #define CLK_ETH_PHY		26
47 #define CLK_ETH_REF_PHYCLK	27
48 #define CLK_FLASH_PROMIP	28
49 #define CLK_MAIN_DISP		29
50 #define CLK_AUX_DISP		30
51 #define CLK_COMPO_DVP		31
52 
53 /* CLOCKGEN D0 */
54 #define CLK_PCM_0		0
55 #define CLK_PCM_1		1
56 #define CLK_PCM_2		2
57 #define CLK_SPDIFF		3
58 
59 /* CLOCKGEN D2 */
60 #define CLK_PIX_MAIN_DISP	0
61 #define CLK_PIX_PIP		1
62 #define CLK_PIX_GDP1		2
63 #define CLK_PIX_GDP2		3
64 #define CLK_PIX_GDP3		4
65 #define CLK_PIX_GDP4		5
66 #define CLK_PIX_AUX_DISP	6
67 #define CLK_DENC		7
68 #define CLK_PIX_HDDAC		8
69 #define CLK_HDDAC		9
70 #define CLK_SDDAC		10
71 #define CLK_PIX_DVO		11
72 #define CLK_DVO			12
73 #define CLK_PIX_HDMI		13
74 #define CLK_TMDS_HDMI		14
75 #define CLK_REF_HDMIPHY		15
76 
77 /* CLOCKGEN D3 */
78 #define CLK_STFE_FRC1		0
79 #define CLK_TSOUT_0		1
80 #define CLK_TSOUT_1		2
81 #define CLK_MCHI		3
82 #define CLK_VSENS_COMPO		4
83 #define CLK_FRC1_REMOTE		5
84 #define CLK_LPC_0		6
85 #define CLK_LPC_1		7
86 #endif
87