1*e3f9dadaSPaul Walmsley /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 26ec4bae1SPaul Walmsley /* 36ec4bae1SPaul Walmsley * Copyright (C) 2018-2019 SiFive, Inc. 46ec4bae1SPaul Walmsley * Wesley Terpstra 56ec4bae1SPaul Walmsley * Paul Walmsley 66ec4bae1SPaul Walmsley */ 76ec4bae1SPaul Walmsley 86ec4bae1SPaul Walmsley #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H 96ec4bae1SPaul Walmsley #define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H 106ec4bae1SPaul Walmsley 116ec4bae1SPaul Walmsley /* Clock indexes for use by Device Tree data and the PRCI driver */ 126ec4bae1SPaul Walmsley 136ec4bae1SPaul Walmsley #define PRCI_CLK_COREPLL 0 146ec4bae1SPaul Walmsley #define PRCI_CLK_DDRPLL 1 156ec4bae1SPaul Walmsley #define PRCI_CLK_GEMGXLPLL 2 166ec4bae1SPaul Walmsley #define PRCI_CLK_TLCLK 3 176ec4bae1SPaul Walmsley 186ec4bae1SPaul Walmsley #endif 19