1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Xing Zheng <zhengxing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 18 19 /* core clocks */ 20 #define PLL_APLLL 1 21 #define PLL_APLLB 2 22 #define PLL_DPLL 3 23 #define PLL_CPLL 4 24 #define PLL_GPLL 5 25 #define PLL_NPLL 6 26 #define PLL_VPLL 7 27 #define ARMCLKL 8 28 #define ARMCLKB 9 29 30 /* sclk gates (special clocks) */ 31 #define SCLK_I2C1 65 32 #define SCLK_I2C2 66 33 #define SCLK_I2C3 67 34 #define SCLK_I2C5 68 35 #define SCLK_I2C6 69 36 #define SCLK_I2C7 70 37 #define SCLK_SPI0 71 38 #define SCLK_SPI1 72 39 #define SCLK_SPI2 73 40 #define SCLK_SPI4 74 41 #define SCLK_SPI5 75 42 #define SCLK_SDMMC 76 43 #define SCLK_SDIO 77 44 #define SCLK_EMMC 78 45 #define SCLK_TSADC 79 46 #define SCLK_SARADC 80 47 #define SCLK_UART0 81 48 #define SCLK_UART1 82 49 #define SCLK_UART2 83 50 #define SCLK_UART3 84 51 #define SCLK_SPDIF_8CH 85 52 #define SCLK_I2S0_8CH 86 53 #define SCLK_I2S1_8CH 87 54 #define SCLK_I2S2_8CH 88 55 #define SCLK_I2S_8CH_OUT 89 56 #define SCLK_TIMER00 90 57 #define SCLK_TIMER01 91 58 #define SCLK_TIMER02 92 59 #define SCLK_TIMER03 93 60 #define SCLK_TIMER04 94 61 #define SCLK_TIMER05 95 62 #define SCLK_TIMER06 96 63 #define SCLK_TIMER07 97 64 #define SCLK_TIMER08 98 65 #define SCLK_TIMER09 99 66 #define SCLK_TIMER10 100 67 #define SCLK_TIMER11 101 68 #define SCLK_MACREF 102 69 #define SCLK_MAC_RX 103 70 #define SCLK_MAC_TX 104 71 #define SCLK_MAC 105 72 #define SCLK_MACREF_OUT 106 73 #define SCLK_VOP0_PWM 107 74 #define SCLK_VOP1_PWM 108 75 #define SCLK_RGA_CORE 109 76 #define SCLK_ISP0 110 77 #define SCLK_ISP1 111 78 #define SCLK_HDMI_CEC 112 79 #define SCLK_HDMI_SFR 113 80 #define SCLK_DP_CORE 114 81 #define SCLK_PVTM_CORE_L 115 82 #define SCLK_PVTM_CORE_B 116 83 #define SCLK_PVTM_GPU 117 84 #define SCLK_PVTM_DDR 118 85 #define SCLK_MIPIDPHY_REF 119 86 #define SCLK_MIPIDPHY_CFG 120 87 #define SCLK_HSICPHY 121 88 #define SCLK_USBPHY480M 122 89 #define SCLK_USB2PHY0_REF 123 90 #define SCLK_USB2PHY1_REF 124 91 #define SCLK_UPHY0_TCPDPHY_REF 125 92 #define SCLK_UPHY0_TCPDCORE 126 93 #define SCLK_UPHY1_TCPDPHY_REF 127 94 #define SCLK_UPHY1_TCPDCORE 128 95 #define SCLK_USB3OTG0_REF 129 96 #define SCLK_USB3OTG1_REF 130 97 #define SCLK_USB3OTG0_SUSPEND 131 98 #define SCLK_USB3OTG1_SUSPEND 132 99 #define SCLK_CRYPTO0 133 100 #define SCLK_CRYPTO1 134 101 #define SCLK_CCI_TRACE 135 102 #define SCLK_CS 136 103 #define SCLK_CIF_OUT 137 104 #define SCLK_PCIEPHY_REF 138 105 #define SCLK_PCIE_CORE 139 106 #define SCLK_M0_PERILP 140 107 #define SCLK_M0_PERILP_DEC 141 108 #define SCLK_CM0S 142 109 #define SCLK_DBG_NOC 143 110 #define SCLK_DBG_PD_CORE_B 144 111 #define SCLK_DBG_PD_CORE_L 145 112 #define SCLK_DFIMON0_TIMER 146 113 #define SCLK_DFIMON1_TIMER 147 114 #define SCLK_INTMEM0 148 115 #define SCLK_INTMEM1 149 116 #define SCLK_INTMEM2 150 117 #define SCLK_INTMEM3 151 118 #define SCLK_INTMEM4 152 119 #define SCLK_INTMEM5 153 120 #define SCLK_SDMMC_DRV 154 121 #define SCLK_SDMMC_SAMPLE 155 122 #define SCLK_SDIO_DRV 156 123 #define SCLK_SDIO_SAMPLE 157 124 #define SCLK_VDU_CORE 158 125 #define SCLK_VDU_CA 159 126 #define SCLK_PCIE_PM 160 127 #define SCLK_SPDIF_REC_DPTX 161 128 #define SCLK_DPHY_PLL 162 129 #define SCLK_DPHY_TX0_CFG 163 130 #define SCLK_DPHY_TX1RX1_CFG 164 131 #define SCLK_DPHY_RX0_CFG 165 132 #define SCLK_RMII_SRC 166 133 #define SCLK_PCIEPHY_REF100M 167 134 #define SCLK_DDRC 168 135 136 #define DCLK_VOP0 180 137 #define DCLK_VOP1 181 138 #define DCLK_VOP0_DIV 182 139 #define DCLK_VOP1_DIV 183 140 #define DCLK_M0_PERILP 184 141 #define DCLK_VOP0_FRAC 185 142 #define DCLK_VOP1_FRAC 186 143 144 #define FCLK_CM0S 190 145 146 /* aclk gates */ 147 #define ACLK_PERIHP 192 148 #define ACLK_PERIHP_NOC 193 149 #define ACLK_PERILP0 194 150 #define ACLK_PERILP0_NOC 195 151 #define ACLK_PERF_PCIE 196 152 #define ACLK_PCIE 197 153 #define ACLK_INTMEM 198 154 #define ACLK_TZMA 199 155 #define ACLK_DCF 200 156 #define ACLK_CCI 201 157 #define ACLK_CCI_NOC0 202 158 #define ACLK_CCI_NOC1 203 159 #define ACLK_CCI_GRF 204 160 #define ACLK_CENTER 205 161 #define ACLK_CENTER_MAIN_NOC 206 162 #define ACLK_CENTER_PERI_NOC 207 163 #define ACLK_GPU 208 164 #define ACLK_PERF_GPU 209 165 #define ACLK_GPU_GRF 210 166 #define ACLK_DMAC0_PERILP 211 167 #define ACLK_DMAC1_PERILP 212 168 #define ACLK_GMAC 213 169 #define ACLK_GMAC_NOC 214 170 #define ACLK_PERF_GMAC 215 171 #define ACLK_VOP0_NOC 216 172 #define ACLK_VOP0 217 173 #define ACLK_VOP1_NOC 218 174 #define ACLK_VOP1 219 175 #define ACLK_RGA 220 176 #define ACLK_RGA_NOC 221 177 #define ACLK_HDCP 222 178 #define ACLK_HDCP_NOC 223 179 #define ACLK_HDCP22 224 180 #define ACLK_IEP 225 181 #define ACLK_IEP_NOC 226 182 #define ACLK_VIO 227 183 #define ACLK_VIO_NOC 228 184 #define ACLK_ISP0 229 185 #define ACLK_ISP1 230 186 #define ACLK_ISP0_NOC 231 187 #define ACLK_ISP1_NOC 232 188 #define ACLK_ISP0_WRAPPER 233 189 #define ACLK_ISP1_WRAPPER 234 190 #define ACLK_VCODEC 235 191 #define ACLK_VCODEC_NOC 236 192 #define ACLK_VDU 237 193 #define ACLK_VDU_NOC 238 194 #define ACLK_PERI 239 195 #define ACLK_EMMC 240 196 #define ACLK_EMMC_CORE 241 197 #define ACLK_EMMC_NOC 242 198 #define ACLK_EMMC_GRF 243 199 #define ACLK_USB3 244 200 #define ACLK_USB3_NOC 245 201 #define ACLK_USB3OTG0 246 202 #define ACLK_USB3OTG1 247 203 #define ACLK_USB3_RKSOC_AXI_PERF 248 204 #define ACLK_USB3_GRF 249 205 #define ACLK_GIC 250 206 #define ACLK_GIC_NOC 251 207 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252 208 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253 209 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254 210 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255 211 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 212 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 213 #define ACLK_ADB400M_PD_CORE_L 258 214 #define ACLK_ADB400M_PD_CORE_B 259 215 #define ACLK_PERF_CORE_L 260 216 #define ACLK_PERF_CORE_B 261 217 #define ACLK_GIC_PRE 262 218 #define ACLK_VOP0_PRE 263 219 #define ACLK_VOP1_PRE 264 220 221 /* pclk gates */ 222 #define PCLK_PERIHP 320 223 #define PCLK_PERIHP_NOC 321 224 #define PCLK_PERILP0 322 225 #define PCLK_PERILP1 323 226 #define PCLK_PERILP1_NOC 324 227 #define PCLK_PERILP_SGRF 325 228 #define PCLK_PERIHP_GRF 326 229 #define PCLK_PCIE 327 230 #define PCLK_SGRF 328 231 #define PCLK_INTR_ARB 329 232 #define PCLK_CENTER_MAIN_NOC 330 233 #define PCLK_CIC 331 234 #define PCLK_COREDBG_B 332 235 #define PCLK_COREDBG_L 333 236 #define PCLK_DBG_CXCS_PD_CORE_B 334 237 #define PCLK_DCF 335 238 #define PCLK_GPIO2 336 239 #define PCLK_GPIO3 337 240 #define PCLK_GPIO4 338 241 #define PCLK_GRF 339 242 #define PCLK_HSICPHY 340 243 #define PCLK_I2C1 341 244 #define PCLK_I2C2 342 245 #define PCLK_I2C3 343 246 #define PCLK_I2C5 344 247 #define PCLK_I2C6 345 248 #define PCLK_I2C7 346 249 #define PCLK_SPI0 347 250 #define PCLK_SPI1 348 251 #define PCLK_SPI2 349 252 #define PCLK_SPI4 350 253 #define PCLK_SPI5 351 254 #define PCLK_UART0 352 255 #define PCLK_UART1 353 256 #define PCLK_UART2 354 257 #define PCLK_UART3 355 258 #define PCLK_TSADC 356 259 #define PCLK_SARADC 357 260 #define PCLK_GMAC 358 261 #define PCLK_GMAC_NOC 359 262 #define PCLK_TIMER0 360 263 #define PCLK_TIMER1 361 264 #define PCLK_EDP 362 265 #define PCLK_EDP_NOC 363 266 #define PCLK_EDP_CTRL 364 267 #define PCLK_VIO 365 268 #define PCLK_VIO_NOC 366 269 #define PCLK_VIO_GRF 367 270 #define PCLK_MIPI_DSI0 368 271 #define PCLK_MIPI_DSI1 369 272 #define PCLK_HDCP 370 273 #define PCLK_HDCP_NOC 371 274 #define PCLK_HDMI_CTRL 372 275 #define PCLK_DP_CTRL 373 276 #define PCLK_HDCP22 374 277 #define PCLK_GASKET 375 278 #define PCLK_DDR 376 279 #define PCLK_DDR_MON 377 280 #define PCLK_DDR_SGRF 378 281 #define PCLK_ISP1_WRAPPER 379 282 #define PCLK_WDT 380 283 #define PCLK_EFUSE1024NS 381 284 #define PCLK_EFUSE1024S 382 285 #define PCLK_PMU_INTR_ARB 383 286 #define PCLK_MAILBOX0 384 287 #define PCLK_USBPHY_MUX_G 385 288 #define PCLK_UPHY0_TCPHY_G 386 289 #define PCLK_UPHY0_TCPD_G 387 290 #define PCLK_UPHY1_TCPHY_G 388 291 #define PCLK_UPHY1_TCPD_G 389 292 #define PCLK_ALIVE 390 293 294 /* hclk gates */ 295 #define HCLK_PERIHP 448 296 #define HCLK_PERILP0 449 297 #define HCLK_PERILP1 450 298 #define HCLK_PERILP0_NOC 451 299 #define HCLK_PERILP1_NOC 452 300 #define HCLK_M0_PERILP 453 301 #define HCLK_M0_PERILP_NOC 454 302 #define HCLK_AHB1TOM 455 303 #define HCLK_HOST0 456 304 #define HCLK_HOST0_ARB 457 305 #define HCLK_HOST1 458 306 #define HCLK_HOST1_ARB 459 307 #define HCLK_HSIC 460 308 #define HCLK_SD 461 309 #define HCLK_SDMMC 462 310 #define HCLK_SDMMC_NOC 463 311 #define HCLK_M_CRYPTO0 464 312 #define HCLK_M_CRYPTO1 465 313 #define HCLK_S_CRYPTO0 466 314 #define HCLK_S_CRYPTO1 467 315 #define HCLK_I2S0_8CH 468 316 #define HCLK_I2S1_8CH 469 317 #define HCLK_I2S2_8CH 470 318 #define HCLK_SPDIF 471 319 #define HCLK_VOP0_NOC 472 320 #define HCLK_VOP0 473 321 #define HCLK_VOP1_NOC 474 322 #define HCLK_VOP1 475 323 #define HCLK_ROM 476 324 #define HCLK_IEP 477 325 #define HCLK_IEP_NOC 478 326 #define HCLK_ISP0 479 327 #define HCLK_ISP1 480 328 #define HCLK_ISP0_NOC 481 329 #define HCLK_ISP1_NOC 482 330 #define HCLK_ISP0_WRAPPER 483 331 #define HCLK_ISP1_WRAPPER 484 332 #define HCLK_RGA 485 333 #define HCLK_RGA_NOC 486 334 #define HCLK_HDCP 487 335 #define HCLK_HDCP_NOC 488 336 #define HCLK_HDCP22 489 337 #define HCLK_VCODEC 490 338 #define HCLK_VCODEC_NOC 491 339 #define HCLK_VDU 492 340 #define HCLK_VDU_NOC 493 341 #define HCLK_SDIO 494 342 #define HCLK_SDIO_NOC 495 343 #define HCLK_SDIOAUDIO_NOC 496 344 345 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) 346 347 /* pmu-clocks indices */ 348 349 #define PLL_PPLL 1 350 351 #define SCLK_32K_SUSPEND_PMU 2 352 #define SCLK_SPI3_PMU 3 353 #define SCLK_TIMER12_PMU 4 354 #define SCLK_TIMER13_PMU 5 355 #define SCLK_UART4_PMU 6 356 #define SCLK_PVTM_PMU 7 357 #define SCLK_WIFI_PMU 8 358 #define SCLK_I2C0_PMU 9 359 #define SCLK_I2C4_PMU 10 360 #define SCLK_I2C8_PMU 11 361 362 #define PCLK_SRC_PMU 19 363 #define PCLK_PMU 20 364 #define PCLK_PMUGRF_PMU 21 365 #define PCLK_INTMEM1_PMU 22 366 #define PCLK_GPIO0_PMU 23 367 #define PCLK_GPIO1_PMU 24 368 #define PCLK_SGRF_PMU 25 369 #define PCLK_NOC_PMU 26 370 #define PCLK_I2C0_PMU 27 371 #define PCLK_I2C4_PMU 28 372 #define PCLK_I2C8_PMU 29 373 #define PCLK_RKPWM_PMU 30 374 #define PCLK_SPI3_PMU 31 375 #define PCLK_TIMER_PMU 32 376 #define PCLK_MAILBOX_PMU 33 377 #define PCLK_UART4_PMU 34 378 #define PCLK_WDT_M0_PMU 35 379 380 #define FCLK_CM0S_SRC_PMU 44 381 #define FCLK_CM0S_PMU 45 382 #define SCLK_CM0S_PMU 46 383 #define HCLK_CM0S_PMU 47 384 #define DCLK_CM0S_PMU 48 385 #define PCLK_INTR_ARB_PMU 49 386 #define HCLK_NOC_PMU 50 387 388 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) 389 390 /* soft-reset indices */ 391 392 /* cru_softrst_con0 */ 393 #define SRST_CORE_L0 0 394 #define SRST_CORE_B0 1 395 #define SRST_CORE_PO_L0 2 396 #define SRST_CORE_PO_B0 3 397 #define SRST_L2_L 4 398 #define SRST_L2_B 5 399 #define SRST_ADB_L 6 400 #define SRST_ADB_B 7 401 #define SRST_A_CCI 8 402 #define SRST_A_CCIM0_NOC 9 403 #define SRST_A_CCIM1_NOC 10 404 #define SRST_DBG_NOC 11 405 406 /* cru_softrst_con1 */ 407 #define SRST_CORE_L0_T 16 408 #define SRST_CORE_L1 17 409 #define SRST_CORE_L2 18 410 #define SRST_CORE_L3 19 411 #define SRST_CORE_PO_L0_T 20 412 #define SRST_CORE_PO_L1 21 413 #define SRST_CORE_PO_L2 22 414 #define SRST_CORE_PO_L3 23 415 #define SRST_A_ADB400_GIC2COREL 24 416 #define SRST_A_ADB400_COREL2GIC 25 417 #define SRST_P_DBG_L 26 418 #define SRST_L2_L_T 28 419 #define SRST_ADB_L_T 29 420 #define SRST_A_RKPERF_L 30 421 #define SRST_PVTM_CORE_L 31 422 423 /* cru_softrst_con2 */ 424 #define SRST_CORE_B0_T 32 425 #define SRST_CORE_B1 33 426 #define SRST_CORE_PO_B0_T 36 427 #define SRST_CORE_PO_B1 37 428 #define SRST_A_ADB400_GIC2COREB 40 429 #define SRST_A_ADB400_COREB2GIC 41 430 #define SRST_P_DBG_B 42 431 #define SRST_L2_B_T 43 432 #define SRST_ADB_B_T 45 433 #define SRST_A_RKPERF_B 46 434 #define SRST_PVTM_CORE_B 47 435 436 /* cru_softrst_con3 */ 437 #define SRST_A_CCI_T 50 438 #define SRST_A_CCIM0_NOC_T 51 439 #define SRST_A_CCIM1_NOC_T 52 440 #define SRST_A_ADB400M_PD_CORE_B_T 53 441 #define SRST_A_ADB400M_PD_CORE_L_T 54 442 #define SRST_DBG_NOC_T 55 443 #define SRST_DBG_CXCS 56 444 #define SRST_CCI_TRACE 57 445 #define SRST_P_CCI_GRF 58 446 447 /* cru_softrst_con4 */ 448 #define SRST_A_CENTER_MAIN_NOC 64 449 #define SRST_A_CENTER_PERI_NOC 65 450 #define SRST_P_CENTER_MAIN 66 451 #define SRST_P_DDRMON 67 452 #define SRST_P_CIC 68 453 #define SRST_P_CENTER_SGRF 69 454 #define SRST_DDR0_MSCH 70 455 #define SRST_DDRCFG0_MSCH 71 456 #define SRST_DDR0 72 457 #define SRST_DDRPHY0 73 458 #define SRST_DDR1_MSCH 74 459 #define SRST_DDRCFG1_MSCH 75 460 #define SRST_DDR1 76 461 #define SRST_DDRPHY1 77 462 #define SRST_DDR_CIC 78 463 #define SRST_PVTM_DDR 79 464 465 /* cru_softrst_con5 */ 466 #define SRST_A_VCODEC_NOC 80 467 #define SRST_A_VCODEC 81 468 #define SRST_H_VCODEC_NOC 82 469 #define SRST_H_VCODEC 83 470 #define SRST_A_VDU_NOC 88 471 #define SRST_A_VDU 89 472 #define SRST_H_VDU_NOC 90 473 #define SRST_H_VDU 91 474 #define SRST_VDU_CORE 92 475 #define SRST_VDU_CA 93 476 477 /* cru_softrst_con6 */ 478 #define SRST_A_IEP_NOC 96 479 #define SRST_A_VOP_IEP 97 480 #define SRST_A_IEP 98 481 #define SRST_H_IEP_NOC 99 482 #define SRST_H_IEP 100 483 #define SRST_A_RGA_NOC 102 484 #define SRST_A_RGA 103 485 #define SRST_H_RGA_NOC 104 486 #define SRST_H_RGA 105 487 #define SRST_RGA_CORE 106 488 #define SRST_EMMC_NOC 108 489 #define SRST_EMMC 109 490 #define SRST_EMMC_GRF 110 491 492 /* cru_softrst_con7 */ 493 #define SRST_A_PERIHP_NOC 112 494 #define SRST_P_PERIHP_GRF 113 495 #define SRST_H_PERIHP_NOC 114 496 #define SRST_USBHOST0 115 497 #define SRST_HOSTC0_AUX 116 498 #define SRST_HOST0_ARB 117 499 #define SRST_USBHOST1 118 500 #define SRST_HOSTC1_AUX 119 501 #define SRST_HOST1_ARB 120 502 #define SRST_SDIO0 121 503 #define SRST_SDMMC 122 504 #define SRST_HSIC 123 505 #define SRST_HSIC_AUX 124 506 #define SRST_AHB1TOM 125 507 #define SRST_P_PERIHP_NOC 126 508 #define SRST_HSICPHY 127 509 510 /* cru_softrst_con8 */ 511 #define SRST_A_PCIE 128 512 #define SRST_P_PCIE 129 513 #define SRST_PCIE_CORE 130 514 #define SRST_PCIE_MGMT 131 515 #define SRST_PCIE_MGMT_STICKY 132 516 #define SRST_PCIE_PIPE 133 517 #define SRST_PCIE_PM 134 518 #define SRST_PCIEPHY 135 519 #define SRST_A_GMAC_NOC 136 520 #define SRST_A_GMAC 137 521 #define SRST_P_GMAC_NOC 138 522 #define SRST_P_GMAC_GRF 140 523 #define SRST_HSICPHY_POR 142 524 #define SRST_HSICPHY_UTMI 143 525 526 /* cru_softrst_con9 */ 527 #define SRST_USB2PHY0_POR 144 528 #define SRST_USB2PHY0_UTMI_PORT0 145 529 #define SRST_USB2PHY0_UTMI_PORT1 146 530 #define SRST_USB2PHY0_EHCIPHY 147 531 #define SRST_UPHY0_PIPE_L00 148 532 #define SRST_UPHY0 149 533 #define SRST_UPHY0_TCPDPWRUP 150 534 #define SRST_USB2PHY1_POR 152 535 #define SRST_USB2PHY1_UTMI_PORT0 153 536 #define SRST_USB2PHY1_UTMI_PORT1 154 537 #define SRST_USB2PHY1_EHCIPHY 155 538 #define SRST_UPHY1_PIPE_L00 156 539 #define SRST_UPHY1 157 540 #define SRST_UPHY1_TCPDPWRUP 158 541 542 /* cru_softrst_con10 */ 543 #define SRST_A_PERILP0_NOC 160 544 #define SRST_A_DCF 161 545 #define SRST_GIC500 162 546 #define SRST_DMAC0_PERILP0 163 547 #define SRST_DMAC1_PERILP0 164 548 #define SRST_TZMA 165 549 #define SRST_INTMEM 166 550 #define SRST_ADB400_MST0 167 551 #define SRST_ADB400_MST1 168 552 #define SRST_ADB400_SLV0 169 553 #define SRST_ADB400_SLV1 170 554 #define SRST_H_PERILP0 171 555 #define SRST_H_PERILP0_NOC 172 556 #define SRST_ROM 173 557 #define SRST_CRYPTO_S 174 558 #define SRST_CRYPTO_M 175 559 560 /* cru_softrst_con11 */ 561 #define SRST_P_DCF 176 562 #define SRST_CM0S_NOC 177 563 #define SRST_CM0S 178 564 #define SRST_CM0S_DBG 179 565 #define SRST_CM0S_PO 180 566 #define SRST_CRYPTO 181 567 #define SRST_P_PERILP1_SGRF 182 568 #define SRST_P_PERILP1_GRF 183 569 #define SRST_CRYPTO1_S 184 570 #define SRST_CRYPTO1_M 185 571 #define SRST_CRYPTO1 186 572 #define SRST_GIC_NOC 188 573 #define SRST_SD_NOC 189 574 #define SRST_SDIOAUDIO_BRG 190 575 576 /* cru_softrst_con12 */ 577 #define SRST_H_PERILP1 192 578 #define SRST_H_PERILP1_NOC 193 579 #define SRST_H_I2S0_8CH 194 580 #define SRST_H_I2S1_8CH 195 581 #define SRST_H_I2S2_8CH 196 582 #define SRST_H_SPDIF_8CH 197 583 #define SRST_P_PERILP1_NOC 198 584 #define SRST_P_EFUSE_1024 199 585 #define SRST_P_EFUSE_1024S 200 586 #define SRST_P_I2C0 201 587 #define SRST_P_I2C1 202 588 #define SRST_P_I2C2 203 589 #define SRST_P_I2C3 204 590 #define SRST_P_I2C4 205 591 #define SRST_P_I2C5 206 592 #define SRST_P_MAILBOX0 207 593 594 /* cru_softrst_con13 */ 595 #define SRST_P_UART0 208 596 #define SRST_P_UART1 209 597 #define SRST_P_UART2 210 598 #define SRST_P_UART3 211 599 #define SRST_P_SARADC 212 600 #define SRST_P_TSADC 213 601 #define SRST_P_SPI0 214 602 #define SRST_P_SPI1 215 603 #define SRST_P_SPI2 216 604 #define SRST_P_SPI3 217 605 #define SRST_P_SPI4 218 606 #define SRST_SPI0 219 607 #define SRST_SPI1 220 608 #define SRST_SPI2 221 609 #define SRST_SPI3 222 610 #define SRST_SPI4 223 611 612 /* cru_softrst_con14 */ 613 #define SRST_I2S0_8CH 224 614 #define SRST_I2S1_8CH 225 615 #define SRST_I2S2_8CH 226 616 #define SRST_SPDIF_8CH 227 617 #define SRST_UART0 228 618 #define SRST_UART1 229 619 #define SRST_UART2 230 620 #define SRST_UART3 231 621 #define SRST_TSADC 232 622 #define SRST_I2C0 233 623 #define SRST_I2C1 234 624 #define SRST_I2C2 235 625 #define SRST_I2C3 236 626 #define SRST_I2C4 237 627 #define SRST_I2C5 238 628 #define SRST_SDIOAUDIO_NOC 239 629 630 /* cru_softrst_con15 */ 631 #define SRST_A_VIO_NOC 240 632 #define SRST_A_HDCP_NOC 241 633 #define SRST_A_HDCP 242 634 #define SRST_H_HDCP_NOC 243 635 #define SRST_H_HDCP 244 636 #define SRST_P_HDCP_NOC 245 637 #define SRST_P_HDCP 246 638 #define SRST_P_HDMI_CTRL 247 639 #define SRST_P_DP_CTRL 248 640 #define SRST_S_DP_CTRL 249 641 #define SRST_C_DP_CTRL 250 642 #define SRST_P_MIPI_DSI0 251 643 #define SRST_P_MIPI_DSI1 252 644 #define SRST_DP_CORE 253 645 #define SRST_DP_I2S 254 646 647 /* cru_softrst_con16 */ 648 #define SRST_GASKET 256 649 #define SRST_VIO_GRF 258 650 #define SRST_DPTX_SPDIF_REC 259 651 #define SRST_HDMI_CTRL 260 652 #define SRST_HDCP_CTRL 261 653 #define SRST_A_ISP0_NOC 262 654 #define SRST_A_ISP1_NOC 263 655 #define SRST_H_ISP0_NOC 266 656 #define SRST_H_ISP1_NOC 267 657 #define SRST_H_ISP0 268 658 #define SRST_H_ISP1 269 659 #define SRST_ISP0 270 660 #define SRST_ISP1 271 661 662 /* cru_softrst_con17 */ 663 #define SRST_A_VOP0_NOC 272 664 #define SRST_A_VOP1_NOC 273 665 #define SRST_A_VOP0 274 666 #define SRST_A_VOP1 275 667 #define SRST_H_VOP0_NOC 276 668 #define SRST_H_VOP1_NOC 277 669 #define SRST_H_VOP0 278 670 #define SRST_H_VOP1 279 671 #define SRST_D_VOP0 280 672 #define SRST_D_VOP1 281 673 #define SRST_VOP0_PWM 282 674 #define SRST_VOP1_PWM 283 675 #define SRST_P_EDP_NOC 284 676 #define SRST_P_EDP_CTRL 285 677 678 /* cru_softrst_con18 */ 679 #define SRST_A_GPU 288 680 #define SRST_A_GPU_NOC 289 681 #define SRST_A_GPU_GRF 290 682 #define SRST_PVTM_GPU 291 683 #define SRST_A_USB3_NOC 292 684 #define SRST_A_USB3_OTG0 293 685 #define SRST_A_USB3_OTG1 294 686 #define SRST_A_USB3_GRF 295 687 #define SRST_PMU 296 688 689 /* cru_softrst_con19 */ 690 #define SRST_P_TIMER0_5 304 691 #define SRST_TIMER0 305 692 #define SRST_TIMER1 306 693 #define SRST_TIMER2 307 694 #define SRST_TIMER3 308 695 #define SRST_TIMER4 309 696 #define SRST_TIMER5 310 697 #define SRST_P_TIMER6_11 311 698 #define SRST_TIMER6 312 699 #define SRST_TIMER7 313 700 #define SRST_TIMER8 314 701 #define SRST_TIMER9 315 702 #define SRST_TIMER10 316 703 #define SRST_TIMER11 317 704 #define SRST_P_INTR_ARB_PMU 318 705 #define SRST_P_ALIVE_SGRF 319 706 707 /* cru_softrst_con20 */ 708 #define SRST_P_GPIO2 320 709 #define SRST_P_GPIO3 321 710 #define SRST_P_GPIO4 322 711 #define SRST_P_GRF 323 712 #define SRST_P_ALIVE_NOC 324 713 #define SRST_P_WDT0 325 714 #define SRST_P_WDT1 326 715 #define SRST_P_INTR_ARB 327 716 #define SRST_P_UPHY0_DPTX 328 717 #define SRST_P_UPHY0_APB 330 718 #define SRST_P_UPHY0_TCPHY 332 719 #define SRST_P_UPHY1_TCPHY 333 720 #define SRST_P_UPHY0_TCPDCTRL 334 721 #define SRST_P_UPHY1_TCPDCTRL 335 722 723 /* pmu soft-reset indices */ 724 725 /* pmu_cru_softrst_con0 */ 726 #define SRST_P_NOC 0 727 #define SRST_P_INTMEM 1 728 #define SRST_H_CM0S 2 729 #define SRST_H_CM0S_NOC 3 730 #define SRST_DBG_CM0S 4 731 #define SRST_PO_CM0S 5 732 #define SRST_P_SPI6 6 733 #define SRST_SPI6 7 734 #define SRST_P_TIMER_0_1 8 735 #define SRST_P_TIMER_0 9 736 #define SRST_P_TIMER_1 10 737 #define SRST_P_UART4 11 738 #define SRST_UART4 12 739 #define SRST_P_WDT 13 740 741 /* pmu_cru_softrst_con1 */ 742 #define SRST_P_I2C6 16 743 #define SRST_P_I2C7 17 744 #define SRST_P_I2C8 18 745 #define SRST_P_MAILBOX 19 746 #define SRST_P_RKPWM 20 747 #define SRST_P_PMUGRF 21 748 #define SRST_P_SGRF 22 749 #define SRST_P_GPIO0 23 750 #define SRST_P_GPIO1 24 751 #define SRST_P_CRU 25 752 #define SRST_P_INTR 26 753 #define SRST_PVTM 27 754 #define SRST_I2C6 28 755 #define SRST_I2C7 29 756 #define SRST_I2C8 30 757 758 #endif 759