1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 8 9 /* core clocks */ 10 #define PLL_APLLB 1 11 #define PLL_APLLL 2 12 #define PLL_DPLL 3 13 #define PLL_CPLL 4 14 #define PLL_GPLL 5 15 #define PLL_NPLL 6 16 #define ARMCLKB 7 17 #define ARMCLKL 8 18 19 /* sclk gates (special clocks) */ 20 #define SCLK_GPU_CORE 64 21 #define SCLK_SPI0 65 22 #define SCLK_SPI1 66 23 #define SCLK_SPI2 67 24 #define SCLK_SDMMC 68 25 #define SCLK_SDIO0 69 26 #define SCLK_EMMC 71 27 #define SCLK_TSADC 72 28 #define SCLK_SARADC 73 29 #define SCLK_NANDC0 75 30 #define SCLK_UART0 77 31 #define SCLK_UART1 78 32 #define SCLK_UART2 79 33 #define SCLK_UART3 80 34 #define SCLK_UART4 81 35 #define SCLK_I2S_8CH 82 36 #define SCLK_SPDIF_8CH 83 37 #define SCLK_I2S_2CH 84 38 #define SCLK_TIMER00 85 39 #define SCLK_TIMER01 86 40 #define SCLK_TIMER02 87 41 #define SCLK_TIMER03 88 42 #define SCLK_TIMER04 89 43 #define SCLK_TIMER05 90 44 #define SCLK_OTGPHY0 93 45 #define SCLK_OTG_ADP 96 46 #define SCLK_HSICPHY480M 97 47 #define SCLK_HSICPHY12M 98 48 #define SCLK_MACREF 99 49 #define SCLK_VOP0_PWM 100 50 #define SCLK_MAC_RX 102 51 #define SCLK_MAC_TX 103 52 #define SCLK_EDP_24M 104 53 #define SCLK_EDP 105 54 #define SCLK_RGA 106 55 #define SCLK_ISP 107 56 #define SCLK_HDCP 108 57 #define SCLK_HDMI_HDCP 109 58 #define SCLK_HDMI_CEC 110 59 #define SCLK_HEVC_CABAC 111 60 #define SCLK_HEVC_CORE 112 61 #define SCLK_I2S_8CH_OUT 113 62 #define SCLK_SDMMC_DRV 114 63 #define SCLK_SDIO0_DRV 115 64 #define SCLK_EMMC_DRV 117 65 #define SCLK_SDMMC_SAMPLE 118 66 #define SCLK_SDIO0_SAMPLE 119 67 #define SCLK_EMMC_SAMPLE 121 68 #define SCLK_USBPHY480M 122 69 #define SCLK_PVTM_CORE 123 70 #define SCLK_PVTM_GPU 124 71 #define SCLK_PVTM_PMU 125 72 #define SCLK_SFC 126 73 #define SCLK_MAC 127 74 #define SCLK_MACREF_OUT 128 75 #define SCLK_TIMER10 133 76 #define SCLK_TIMER11 134 77 #define SCLK_TIMER12 135 78 #define SCLK_TIMER13 136 79 #define SCLK_TIMER14 137 80 #define SCLK_TIMER15 138 81 #define SCLK_VIP_OUT 139 82 83 #define DCLK_VOP 190 84 #define MCLK_CRYPTO 191 85 86 /* aclk gates */ 87 #define ACLK_GPU_MEM 192 88 #define ACLK_GPU_CFG 193 89 #define ACLK_DMAC_BUS 194 90 #define ACLK_DMAC_PERI 195 91 #define ACLK_PERI_MMU 196 92 #define ACLK_GMAC 197 93 #define ACLK_VOP 198 94 #define ACLK_VOP_IEP 199 95 #define ACLK_RGA 200 96 #define ACLK_HDCP 201 97 #define ACLK_IEP 202 98 #define ACLK_VIO0_NOC 203 99 #define ACLK_VIP 204 100 #define ACLK_ISP 205 101 #define ACLK_VIO1_NOC 206 102 #define ACLK_VIDEO 208 103 #define ACLK_BUS 209 104 #define ACLK_PERI 210 105 106 /* pclk gates */ 107 #define PCLK_GPIO0 320 108 #define PCLK_GPIO1 321 109 #define PCLK_GPIO2 322 110 #define PCLK_GPIO3 323 111 #define PCLK_PMUGRF 324 112 #define PCLK_MAILBOX 325 113 #define PCLK_GRF 329 114 #define PCLK_SGRF 330 115 #define PCLK_PMU 331 116 #define PCLK_I2C0 332 117 #define PCLK_I2C1 333 118 #define PCLK_I2C2 334 119 #define PCLK_I2C3 335 120 #define PCLK_I2C4 336 121 #define PCLK_I2C5 337 122 #define PCLK_SPI0 338 123 #define PCLK_SPI1 339 124 #define PCLK_SPI2 340 125 #define PCLK_UART0 341 126 #define PCLK_UART1 342 127 #define PCLK_UART2 343 128 #define PCLK_UART3 344 129 #define PCLK_UART4 345 130 #define PCLK_TSADC 346 131 #define PCLK_SARADC 347 132 #define PCLK_SIM 348 133 #define PCLK_GMAC 349 134 #define PCLK_PWM0 350 135 #define PCLK_PWM1 351 136 #define PCLK_TIMER0 353 137 #define PCLK_TIMER1 354 138 #define PCLK_EDP_CTRL 355 139 #define PCLK_MIPI_DSI0 356 140 #define PCLK_MIPI_CSI 358 141 #define PCLK_HDCP 359 142 #define PCLK_HDMI_CTRL 360 143 #define PCLK_VIO_H2P 361 144 #define PCLK_BUS 362 145 #define PCLK_PERI 363 146 #define PCLK_DDRUPCTL 364 147 #define PCLK_DDRPHY 365 148 #define PCLK_ISP 366 149 #define PCLK_VIP 367 150 #define PCLK_WDT 368 151 #define PCLK_EFUSE256 369 152 #define PCLK_DPHYRX 370 153 #define PCLK_DPHYTX0 371 154 155 /* hclk gates */ 156 #define HCLK_SFC 448 157 #define HCLK_OTG0 449 158 #define HCLK_HOST0 450 159 #define HCLK_HOST1 451 160 #define HCLK_HSIC 452 161 #define HCLK_NANDC0 453 162 #define HCLK_TSP 455 163 #define HCLK_SDMMC 456 164 #define HCLK_SDIO0 457 165 #define HCLK_EMMC 459 166 #define HCLK_HSADC 460 167 #define HCLK_CRYPTO 461 168 #define HCLK_I2S_2CH 462 169 #define HCLK_I2S_8CH 463 170 #define HCLK_SPDIF 464 171 #define HCLK_VOP 465 172 #define HCLK_ROM 467 173 #define HCLK_IEP 468 174 #define HCLK_ISP 469 175 #define HCLK_RGA 470 176 #define HCLK_VIO_AHB_ARBI 471 177 #define HCLK_VIO_NOC 472 178 #define HCLK_VIP 473 179 #define HCLK_VIO_H2P 474 180 #define HCLK_VIO_HDCPMMU 475 181 #define HCLK_VIDEO 476 182 #define HCLK_BUS 477 183 #define HCLK_PERI 478 184 185 /* soft-reset indices */ 186 #define SRST_CORE_B0 0 187 #define SRST_CORE_B1 1 188 #define SRST_CORE_B2 2 189 #define SRST_CORE_B3 3 190 #define SRST_CORE_B0_PO 4 191 #define SRST_CORE_B1_PO 5 192 #define SRST_CORE_B2_PO 6 193 #define SRST_CORE_B3_PO 7 194 #define SRST_L2_B 8 195 #define SRST_ADB_B 9 196 #define SRST_PD_CORE_B_NIU 10 197 #define SRST_PDBUS_STRSYS 11 198 #define SRST_SOCDBG_B 14 199 #define SRST_CORE_B_DBG 15 200 201 #define SRST_DMAC1 18 202 #define SRST_INTMEM 19 203 #define SRST_ROM 20 204 #define SRST_SPDIF8CH 21 205 #define SRST_I2S8CH 23 206 #define SRST_MAILBOX 24 207 #define SRST_I2S2CH 25 208 #define SRST_EFUSE_256 26 209 #define SRST_MCU_SYS 28 210 #define SRST_MCU_PO 29 211 #define SRST_MCU_NOC 30 212 #define SRST_EFUSE 31 213 214 #define SRST_GPIO0 32 215 #define SRST_GPIO1 33 216 #define SRST_GPIO2 34 217 #define SRST_GPIO3 35 218 #define SRST_GPIO4 36 219 #define SRST_PMUGRF 41 220 #define SRST_I2C0 42 221 #define SRST_I2C1 43 222 #define SRST_I2C2 44 223 #define SRST_I2C3 45 224 #define SRST_I2C4 46 225 #define SRST_I2C5 47 226 227 #define SRST_DWPWM 48 228 #define SRST_MMC_PERI 49 229 #define SRST_PERIPH_MMU 50 230 #define SRST_GRF 55 231 #define SRST_PMU 56 232 #define SRST_PERIPH_AXI 57 233 #define SRST_PERIPH_AHB 58 234 #define SRST_PERIPH_APB 59 235 #define SRST_PERIPH_NIU 60 236 #define SRST_PDPERI_AHB_ARBI 61 237 #define SRST_EMEM 62 238 #define SRST_USB_PERI 63 239 240 #define SRST_DMAC2 64 241 #define SRST_MAC 66 242 #define SRST_GPS 67 243 #define SRST_RKPWM 69 244 #define SRST_USBHOST0 72 245 #define SRST_HSIC 73 246 #define SRST_HSIC_AUX 74 247 #define SRST_HSIC_PHY 75 248 #define SRST_HSADC 76 249 #define SRST_NANDC0 77 250 #define SRST_SFC 79 251 252 #define SRST_SPI0 83 253 #define SRST_SPI1 84 254 #define SRST_SPI2 85 255 #define SRST_SARADC 87 256 #define SRST_PDALIVE_NIU 88 257 #define SRST_PDPMU_INTMEM 89 258 #define SRST_PDPMU_NIU 90 259 #define SRST_SGRF 91 260 261 #define SRST_VIO_ARBI 96 262 #define SRST_RGA_NIU 97 263 #define SRST_VIO0_NIU_AXI 98 264 #define SRST_VIO_NIU_AHB 99 265 #define SRST_LCDC0_AXI 100 266 #define SRST_LCDC0_AHB 101 267 #define SRST_LCDC0_DCLK 102 268 #define SRST_VIP 104 269 #define SRST_RGA_CORE 105 270 #define SRST_IEP_AXI 106 271 #define SRST_IEP_AHB 107 272 #define SRST_RGA_AXI 108 273 #define SRST_RGA_AHB 109 274 #define SRST_ISP 110 275 #define SRST_EDP_24M 111 276 277 #define SRST_VIDEO_AXI 112 278 #define SRST_VIDEO_AHB 113 279 #define SRST_MIPIDPHYTX 114 280 #define SRST_MIPIDSI0 115 281 #define SRST_MIPIDPHYRX 116 282 #define SRST_MIPICSI 117 283 #define SRST_GPU 120 284 #define SRST_HDMI 121 285 #define SRST_EDP 122 286 #define SRST_PMU_PVTM 123 287 #define SRST_CORE_PVTM 124 288 #define SRST_GPU_PVTM 125 289 #define SRST_GPU_SYS 126 290 #define SRST_GPU_MEM_NIU 127 291 292 #define SRST_MMC0 128 293 #define SRST_SDIO0 129 294 #define SRST_EMMC 131 295 #define SRST_USBOTG_AHB 132 296 #define SRST_USBOTG_PHY 133 297 #define SRST_USBOTG_CON 134 298 #define SRST_USBHOST0_AHB 135 299 #define SRST_USBHOST0_PHY 136 300 #define SRST_USBHOST0_CON 137 301 #define SRST_USBOTG_UTMI 138 302 #define SRST_USBHOST1_UTMI 139 303 #define SRST_USB_ADP 141 304 305 #define SRST_CORESIGHT 144 306 #define SRST_PD_CORE_AHB_NOC 145 307 #define SRST_PD_CORE_APB_NOC 146 308 #define SRST_GIC 148 309 #define SRST_LCDC_PWM0 149 310 #define SRST_RGA_H2P_BRG 153 311 #define SRST_VIDEO 154 312 #define SRST_GPU_CFG_NIU 157 313 #define SRST_TSADC 159 314 315 #define SRST_DDRPHY0 160 316 #define SRST_DDRPHY0_APB 161 317 #define SRST_DDRCTRL0 162 318 #define SRST_DDRCTRL0_APB 163 319 #define SRST_VIDEO_NIU 165 320 #define SRST_VIDEO_NIU_AHB 167 321 #define SRST_DDRMSCH0 170 322 #define SRST_PDBUS_AHB 173 323 #define SRST_CRYPTO 174 324 325 #define SRST_UART0 179 326 #define SRST_UART1 180 327 #define SRST_UART2 181 328 #define SRST_UART3 182 329 #define SRST_UART4 183 330 #define SRST_SIMC 186 331 #define SRST_TSP 188 332 #define SRST_TSP_CLKIN0 189 333 334 #define SRST_CORE_L0 192 335 #define SRST_CORE_L1 193 336 #define SRST_CORE_L2 194 337 #define SRST_CORE_L3 195 338 #define SRST_CORE_L0_PO 195 339 #define SRST_CORE_L1_PO 197 340 #define SRST_CORE_L2_PO 198 341 #define SRST_CORE_L3_PO 199 342 #define SRST_L2_L 200 343 #define SRST_ADB_L 201 344 #define SRST_PD_CORE_L_NIU 202 345 #define SRST_CCI_SYS 203 346 #define SRST_CCI_DDR 204 347 #define SRST_CCI 205 348 #define SRST_SOCDBG_L 206 349 #define SRST_CORE_L_DBG 207 350 351 #define SRST_CORE_B0_NC 208 352 #define SRST_CORE_B0_PO_NC 209 353 #define SRST_L2_B_NC 210 354 #define SRST_ADB_B_NC 211 355 #define SRST_PD_CORE_B_NIU_NC 212 356 #define SRST_PDBUS_STRSYS_NC 213 357 #define SRST_CORE_L0_NC 214 358 #define SRST_CORE_L0_PO_NC 215 359 #define SRST_L2_L_NC 216 360 #define SRST_ADB_L_NC 217 361 #define SRST_PD_CORE_L_NIU_NC 218 362 #define SRST_CCI_SYS_NC 219 363 #define SRST_CCI_DDR_NC 220 364 #define SRST_CCI_NC 221 365 #define SRST_TRACE_NC 222 366 367 #define SRST_TIMER00 224 368 #define SRST_TIMER01 225 369 #define SRST_TIMER02 226 370 #define SRST_TIMER03 227 371 #define SRST_TIMER04 228 372 #define SRST_TIMER05 229 373 #define SRST_TIMER10 230 374 #define SRST_TIMER11 231 375 #define SRST_TIMER12 232 376 #define SRST_TIMER13 233 377 #define SRST_TIMER14 234 378 #define SRST_TIMER15 235 379 #define SRST_TIMER0_APB 236 380 #define SRST_TIMER1_APB 237 381 382 #endif 383