1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 /* core clocks from */ 17 #define PLL_APLL 1 18 #define PLL_DPLL 2 19 #define PLL_CPLL 3 20 #define PLL_GPLL 4 21 #define CORE_PERI 5 22 #define CORE_L2C 6 23 24 /* sclk gates (special clocks) */ 25 #define SCLK_UART0 64 26 #define SCLK_UART1 65 27 #define SCLK_UART2 66 28 #define SCLK_UART3 67 29 #define SCLK_MAC 68 30 #define SCLK_SPI0 69 31 #define SCLK_SPI1 70 32 #define SCLK_SARADC 71 33 #define SCLK_SDMMC 72 34 #define SCLK_SDIO 73 35 #define SCLK_EMMC 74 36 #define SCLK_I2S0 75 37 #define SCLK_I2S1 76 38 #define SCLK_I2S2 77 39 #define SCLK_SPDIF 78 40 #define SCLK_CIF0 79 41 #define SCLK_CIF1 80 42 #define SCLK_OTGPHY0 81 43 #define SCLK_OTGPHY1 82 44 #define SCLK_HSADC 83 45 #define SCLK_TIMER0 84 46 #define SCLK_TIMER1 85 47 #define SCLK_TIMER2 86 48 #define SCLK_TIMER3 87 49 #define SCLK_TIMER4 88 50 #define SCLK_TIMER5 89 51 #define SCLK_TIMER6 90 52 #define SCLK_JTAG 91 53 #define SCLK_SMC 92 54 55 #define DCLK_LCDC0 190 56 #define DCLK_LCDC1 191 57 58 /* aclk gates */ 59 #define ACLK_DMA1 192 60 #define ACLK_DMA2 193 61 #define ACLK_GPS 194 62 #define ACLK_LCDC0 195 63 #define ACLK_LCDC1 196 64 #define ACLK_GPU 197 65 #define ACLK_SMC 198 66 #define ACLK_CIF 199 67 #define ACLK_IPP 200 68 #define ACLK_RGA 201 69 #define ACLK_CIF0 202 70 71 /* pclk gates */ 72 #define PCLK_GRF 320 73 #define PCLK_PMU 321 74 #define PCLK_TIMER0 322 75 #define PCLK_TIMER1 323 76 #define PCLK_TIMER2 324 77 #define PCLK_TIMER3 325 78 #define PCLK_PWM01 326 79 #define PCLK_PWM23 327 80 #define PCLK_SPI0 328 81 #define PCLK_SPI1 329 82 #define PCLK_SARADC 330 83 #define PCLK_WDT 331 84 #define PCLK_UART0 332 85 #define PCLK_UART1 333 86 #define PCLK_UART2 334 87 #define PCLK_UART3 335 88 #define PCLK_I2C0 336 89 #define PCLK_I2C1 337 90 #define PCLK_I2C2 338 91 #define PCLK_I2C3 339 92 #define PCLK_I2C4 340 93 #define PCLK_GPIO0 341 94 #define PCLK_GPIO1 342 95 #define PCLK_GPIO2 343 96 #define PCLK_GPIO3 344 97 #define PCLK_GPIO4 345 98 #define PCLK_GPIO6 346 99 #define PCLK_EFUSE 347 100 #define PCLK_TZPC 348 101 #define PCLK_TSADC 349 102 103 /* hclk gates */ 104 #define HCLK_SDMMC 448 105 #define HCLK_SDIO 449 106 #define HCLK_EMMC 450 107 #define HCLK_OTG0 451 108 #define HCLK_EMAC 452 109 #define HCLK_SPDIF 453 110 #define HCLK_I2S0 454 111 #define HCLK_I2S1 455 112 #define HCLK_I2S2 456 113 #define HCLK_OTG1 457 114 #define HCLK_HSIC 458 115 #define HCLK_HSADC 459 116 #define HCLK_PIDF 460 117 #define HCLK_LCDC0 461 118 #define HCLK_LCDC1 462 119 #define HCLK_ROM 463 120 #define HCLK_CIF0 464 121 #define HCLK_IPP 465 122 #define HCLK_RGA 466 123 #define HCLK_NANDC0 467 124 125 #define CLK_NR_CLKS (HCLK_NANDC0 + 1) 126 127 /* soft-reset indices */ 128 #define SRST_MCORE 2 129 #define SRST_CORE0 3 130 #define SRST_CORE1 4 131 #define SRST_MCORE_DBG 7 132 #define SRST_CORE0_DBG 8 133 #define SRST_CORE1_DBG 9 134 #define SRST_CORE0_WDT 12 135 #define SRST_CORE1_WDT 13 136 #define SRST_STRC_SYS 14 137 #define SRST_L2C 15 138 139 #define SRST_CPU_AHB 17 140 #define SRST_AHB2APB 19 141 #define SRST_DMA1 20 142 #define SRST_INTMEM 21 143 #define SRST_ROM 22 144 #define SRST_SPDIF 26 145 #define SRST_TIMER0 27 146 #define SRST_TIMER1 28 147 #define SRST_EFUSE 30 148 149 #define SRST_GPIO0 32 150 #define SRST_GPIO1 33 151 #define SRST_GPIO2 34 152 #define SRST_GPIO3 35 153 154 #define SRST_UART0 39 155 #define SRST_UART1 40 156 #define SRST_UART2 41 157 #define SRST_UART3 42 158 #define SRST_I2C0 43 159 #define SRST_I2C1 44 160 #define SRST_I2C2 45 161 #define SRST_I2C3 46 162 #define SRST_I2C4 47 163 164 #define SRST_PWM0 48 165 #define SRST_PWM1 49 166 #define SRST_DAP_PO 50 167 #define SRST_DAP 51 168 #define SRST_DAP_SYS 52 169 #define SRST_TPIU_ATB 53 170 #define SRST_PMU_APB 54 171 #define SRST_GRF 55 172 #define SRST_PMU 56 173 #define SRST_PERI_AXI 57 174 #define SRST_PERI_AHB 58 175 #define SRST_PERI_APB 59 176 #define SRST_PERI_NIU 60 177 #define SRST_CPU_PERI 61 178 #define SRST_EMEM_PERI 62 179 #define SRST_USB_PERI 63 180 181 #define SRST_DMA2 64 182 #define SRST_SMC 65 183 #define SRST_MAC 66 184 #define SRST_NANC0 68 185 #define SRST_USBOTG0 69 186 #define SRST_USBPHY0 70 187 #define SRST_OTGC0 71 188 #define SRST_USBOTG1 72 189 #define SRST_USBPHY1 73 190 #define SRST_OTGC1 74 191 #define SRST_HSADC 76 192 #define SRST_PIDFILTER 77 193 #define SRST_DDR_MSCH 79 194 195 #define SRST_TZPC 80 196 #define SRST_SDMMC 81 197 #define SRST_SDIO 82 198 #define SRST_EMMC 83 199 #define SRST_SPI0 84 200 #define SRST_SPI1 85 201 #define SRST_WDT 86 202 #define SRST_SARADC 87 203 #define SRST_DDRPHY 88 204 #define SRST_DDRPHY_APB 89 205 #define SRST_DDRCTL 90 206 #define SRST_DDRCTL_APB 91 207 #define SRST_DDRPUB 93 208 209 #define SRST_VIO0_AXI 98 210 #define SRST_VIO0_AHB 99 211 #define SRST_LCDC0_AXI 100 212 #define SRST_LCDC0_AHB 101 213 #define SRST_LCDC0_DCLK 102 214 #define SRST_LCDC1_AXI 103 215 #define SRST_LCDC1_AHB 104 216 #define SRST_LCDC1_DCLK 105 217 #define SRST_IPP_AXI 106 218 #define SRST_IPP_AHB 107 219 #define SRST_RGA_AXI 108 220 #define SRST_RGA_AHB 109 221 #define SRST_CIF0 110 222 223 #define SRST_VCODEC_AXI 112 224 #define SRST_VCODEC_AHB 113 225 #define SRST_VIO1_AXI 114 226 #define SRST_VCODEC_CPU 115 227 #define SRST_VCODEC_NIU 116 228 #define SRST_GPU 120 229 #define SRST_GPU_NIU 122 230 #define SRST_TFUN_ATB 125 231 #define SRST_TFUN_APB 126 232 #define SRST_CTI4_APB 127 233 234 #define SRST_TPIU_APB 128 235 #define SRST_TRACE 129 236 #define SRST_CORE_DBG 130 237 #define SRST_DBG_APB 131 238 #define SRST_CTI0 132 239 #define SRST_CTI0_APB 133 240 #define SRST_CTI1 134 241 #define SRST_CTI1_APB 135 242 #define SRST_PTM_CORE0 136 243 #define SRST_PTM_CORE1 137 244 #define SRST_PTM0 138 245 #define SRST_PTM0_ATB 139 246 #define SRST_PTM1 140 247 #define SRST_PTM1_ATB 141 248 #define SRST_CTM 142 249 #define SRST_TS 143 250