1292bf6c5SLad Prabhakar /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2292bf6c5SLad Prabhakar * 3292bf6c5SLad Prabhakar * Copyright (C) 2025 Renesas Electronics Corp. 4292bf6c5SLad Prabhakar */ 5292bf6c5SLad Prabhakar 6292bf6c5SLad Prabhakar #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ 7292bf6c5SLad Prabhakar #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ 8292bf6c5SLad Prabhakar 9292bf6c5SLad Prabhakar #include <dt-bindings/clock/renesas-cpg-mssr.h> 10292bf6c5SLad Prabhakar 11292bf6c5SLad Prabhakar /* R9A09G087 CPG Core Clocks */ 12292bf6c5SLad Prabhakar #define R9A09G087_CLK_CA55C0 0 13292bf6c5SLad Prabhakar #define R9A09G087_CLK_CA55C1 1 14292bf6c5SLad Prabhakar #define R9A09G087_CLK_CA55C2 2 15292bf6c5SLad Prabhakar #define R9A09G087_CLK_CA55C3 3 16292bf6c5SLad Prabhakar #define R9A09G087_CLK_CA55S 4 17292bf6c5SLad Prabhakar #define R9A09G087_CLK_CR52_CPU0 5 18292bf6c5SLad Prabhakar #define R9A09G087_CLK_CR52_CPU1 6 19292bf6c5SLad Prabhakar #define R9A09G087_CLK_CKIO 7 20292bf6c5SLad Prabhakar #define R9A09G087_CLK_PCLKAH 8 21292bf6c5SLad Prabhakar #define R9A09G087_CLK_PCLKAM 9 22292bf6c5SLad Prabhakar #define R9A09G087_CLK_PCLKAL 10 23292bf6c5SLad Prabhakar #define R9A09G087_CLK_PCLKGPTL 11 24292bf6c5SLad Prabhakar #define R9A09G087_CLK_PCLKH 12 25292bf6c5SLad Prabhakar #define R9A09G087_CLK_PCLKM 13 26292bf6c5SLad Prabhakar #define R9A09G087_CLK_PCLKL 14 27*2a76193fSLad Prabhakar #define R9A09G087_SDHI_CLKHS 15 28292bf6c5SLad Prabhakar 29292bf6c5SLad Prabhakar #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ 30