1*4e591b89SThierry Bultel /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4e591b89SThierry Bultel * 3*4e591b89SThierry Bultel * Copyright (C) 2025 Renesas Electronics Corp. 4*4e591b89SThierry Bultel */ 5*4e591b89SThierry Bultel 6*4e591b89SThierry Bultel #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 7*4e591b89SThierry Bultel #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 8*4e591b89SThierry Bultel 9*4e591b89SThierry Bultel #include <dt-bindings/clock/renesas-cpg-mssr.h> 10*4e591b89SThierry Bultel 11*4e591b89SThierry Bultel /* R9A09G077 CPG Core Clocks */ 12*4e591b89SThierry Bultel #define R9A09G077_CLK_CA55C0 0 13*4e591b89SThierry Bultel #define R9A09G077_CLK_CA55C1 1 14*4e591b89SThierry Bultel #define R9A09G077_CLK_CA55C2 2 15*4e591b89SThierry Bultel #define R9A09G077_CLK_CA55C3 3 16*4e591b89SThierry Bultel #define R9A09G077_CLK_CA55S 4 17*4e591b89SThierry Bultel #define R9A09G077_CLK_CR52_CPU0 5 18*4e591b89SThierry Bultel #define R9A09G077_CLK_CR52_CPU1 6 19*4e591b89SThierry Bultel #define R9A09G077_CLK_CKIO 7 20*4e591b89SThierry Bultel #define R9A09G077_CLK_PCLKAH 8 21*4e591b89SThierry Bultel #define R9A09G077_CLK_PCLKAM 9 22*4e591b89SThierry Bultel #define R9A09G077_CLK_PCLKAL 10 23*4e591b89SThierry Bultel #define R9A09G077_CLK_PCLKGPTL 11 24*4e591b89SThierry Bultel #define R9A09G077_CLK_PCLKH 12 25*4e591b89SThierry Bultel #define R9A09G077_CLK_PCLKM 13 26*4e591b89SThierry Bultel 27*4e591b89SThierry Bultel #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ 28