1c04269c0SLad Prabhakar /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2c04269c0SLad Prabhakar * 3c04269c0SLad Prabhakar * Copyright (C) 2025 Renesas Electronics Corp. 4c04269c0SLad Prabhakar */ 5c04269c0SLad Prabhakar #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 6c04269c0SLad Prabhakar #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 7c04269c0SLad Prabhakar 8c04269c0SLad Prabhakar #include <dt-bindings/clock/renesas-cpg-mssr.h> 9c04269c0SLad Prabhakar 10c04269c0SLad Prabhakar /* Core Clock list */ 11c04269c0SLad Prabhakar #define R9A09G056_SYS_0_PCLK 0 12c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK0 1 13c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK1 2 14c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK2 3 15c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK3 4 16c04269c0SLad Prabhakar #define R9A09G056_CA55_0_PERIPHCLK 5 17c04269c0SLad Prabhakar #define R9A09G056_CM33_CLK0 6 18c04269c0SLad Prabhakar #define R9A09G056_CST_0_SWCLKTCK 7 19c04269c0SLad Prabhakar #define R9A09G056_IOTOP_0_SHCLK 8 20c04269c0SLad Prabhakar #define R9A09G056_USB2_0_CLK_CORE0 9 21c04269c0SLad Prabhakar #define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 22c04269c0SLad Prabhakar #define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 23*5e4e8c14SLad Prabhakar #define R9A09G056_SPI_CLK_SPI 12 24c04269c0SLad Prabhakar 25c04269c0SLad Prabhakar #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ 26