1*ecadea00SSergei Shtylyov /* 2*ecadea00SSergei Shtylyov * Copyright (C) 2016 Renesas Electronics Corp. 3*ecadea00SSergei Shtylyov * Copyright (C) 2017 Cogent Embedded, Inc. 4*ecadea00SSergei Shtylyov * 5*ecadea00SSergei Shtylyov * This program is free software; you can redistribute it and/or modify 6*ecadea00SSergei Shtylyov * it under the terms of the GNU General Public License as published by 7*ecadea00SSergei Shtylyov * the Free Software Foundation; either version 2 of the License, or 8*ecadea00SSergei Shtylyov * (at your option) any later version. 9*ecadea00SSergei Shtylyov */ 10*ecadea00SSergei Shtylyov #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 11*ecadea00SSergei Shtylyov #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 12*ecadea00SSergei Shtylyov 13*ecadea00SSergei Shtylyov #include <dt-bindings/clock/renesas-cpg-mssr.h> 14*ecadea00SSergei Shtylyov 15*ecadea00SSergei Shtylyov /* r8a77970 CPG Core Clocks */ 16*ecadea00SSergei Shtylyov #define R8A77970_CLK_Z2 0 17*ecadea00SSergei Shtylyov #define R8A77970_CLK_ZR 1 18*ecadea00SSergei Shtylyov #define R8A77970_CLK_ZTR 2 19*ecadea00SSergei Shtylyov #define R8A77970_CLK_ZTRD2 3 20*ecadea00SSergei Shtylyov #define R8A77970_CLK_ZT 4 21*ecadea00SSergei Shtylyov #define R8A77970_CLK_ZX 5 22*ecadea00SSergei Shtylyov #define R8A77970_CLK_S1D1 6 23*ecadea00SSergei Shtylyov #define R8A77970_CLK_S1D2 7 24*ecadea00SSergei Shtylyov #define R8A77970_CLK_S1D4 8 25*ecadea00SSergei Shtylyov #define R8A77970_CLK_S2D1 9 26*ecadea00SSergei Shtylyov #define R8A77970_CLK_S2D2 10 27*ecadea00SSergei Shtylyov #define R8A77970_CLK_S2D4 11 28*ecadea00SSergei Shtylyov #define R8A77970_CLK_LB 12 29*ecadea00SSergei Shtylyov #define R8A77970_CLK_CL 13 30*ecadea00SSergei Shtylyov #define R8A77970_CLK_ZB3 14 31*ecadea00SSergei Shtylyov #define R8A77970_CLK_ZB3D2 15 32*ecadea00SSergei Shtylyov #define R8A77970_CLK_DDR 16 33*ecadea00SSergei Shtylyov #define R8A77970_CLK_CR 17 34*ecadea00SSergei Shtylyov #define R8A77970_CLK_CRD2 18 35*ecadea00SSergei Shtylyov #define R8A77970_CLK_SD0H 19 36*ecadea00SSergei Shtylyov #define R8A77970_CLK_SD0 20 37*ecadea00SSergei Shtylyov #define R8A77970_CLK_RPC 21 38*ecadea00SSergei Shtylyov #define R8A77970_CLK_RPCD2 22 39*ecadea00SSergei Shtylyov #define R8A77970_CLK_MSO 23 40*ecadea00SSergei Shtylyov #define R8A77970_CLK_CANFD 24 41*ecadea00SSergei Shtylyov #define R8A77970_CLK_CSI0 25 42*ecadea00SSergei Shtylyov #define R8A77970_CLK_FRAY 26 43*ecadea00SSergei Shtylyov #define R8A77970_CLK_CP 27 44*ecadea00SSergei Shtylyov #define R8A77970_CLK_CPEX 28 45*ecadea00SSergei Shtylyov #define R8A77970_CLK_R 29 46*ecadea00SSergei Shtylyov #define R8A77970_CLK_OSC 30 47*ecadea00SSergei Shtylyov 48*ecadea00SSergei Shtylyov #endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ 49