1*0b05ad22SGeert Uytterhoeven /* SPDX-License-Identifier: GPL-2.0+ 2*0b05ad22SGeert Uytterhoeven * 3*0b05ad22SGeert Uytterhoeven * Copyright (C) 2019 Renesas Electronics Corp. 4*0b05ad22SGeert Uytterhoeven */ 5*0b05ad22SGeert Uytterhoeven #ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ 6*0b05ad22SGeert Uytterhoeven #define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ 7*0b05ad22SGeert Uytterhoeven 8*0b05ad22SGeert Uytterhoeven #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*0b05ad22SGeert Uytterhoeven 10*0b05ad22SGeert Uytterhoeven /* r8a77961 CPG Core Clocks */ 11*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_Z 0 12*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_Z2 1 13*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZR 2 14*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZG 3 15*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZTR 4 16*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZTRD2 5 17*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZT 6 18*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZX 7 19*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D1 8 20*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D2 9 21*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D3 10 22*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D4 11 23*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D6 12 24*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D8 13 25*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D12 14 26*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S1D1 15 27*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S1D2 16 28*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S1D4 17 29*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S2D1 18 30*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S2D2 19 31*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S2D4 20 32*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S3D1 21 33*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S3D2 22 34*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S3D4 23 35*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_LB 24 36*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CL 25 37*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZB3 26 38*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZB3D2 27 39*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZB3D4 28 40*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CR 29 41*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CRD2 30 42*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD0H 31 43*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD0 32 44*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD1H 33 45*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD1 34 46*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD2H 35 47*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD2 36 48*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD3H 37 49*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD3 38 50*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SSP2 39 51*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SSP1 40 52*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SSPRS 41 53*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_RPC 42 54*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_RPCD2 43 55*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_MSO 44 56*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CANFD 45 57*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_HDMI 46 58*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CSI0 47 59*0b05ad22SGeert Uytterhoeven /* CLK_CSIREF was removed */ 60*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CP 49 61*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CPEX 50 62*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_R 51 63*0b05ad22SGeert Uytterhoeven #define R8A77961_CLK_OSC 52 64*0b05ad22SGeert Uytterhoeven 65*0b05ad22SGeert Uytterhoeven #endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ 66