1*0ea86f5aSGeert Uytterhoeven /* 2*0ea86f5aSGeert Uytterhoeven * Copyright (C) 2015 Renesas Electronics Corp. 3*0ea86f5aSGeert Uytterhoeven * 4*0ea86f5aSGeert Uytterhoeven * This program is free software; you can redistribute it and/or modify 5*0ea86f5aSGeert Uytterhoeven * it under the terms of the GNU General Public License as published by 6*0ea86f5aSGeert Uytterhoeven * the Free Software Foundation; either version 2 of the License, or 7*0ea86f5aSGeert Uytterhoeven * (at your option) any later version. 8*0ea86f5aSGeert Uytterhoeven */ 9*0ea86f5aSGeert Uytterhoeven 10*0ea86f5aSGeert Uytterhoeven #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 11*0ea86f5aSGeert Uytterhoeven #define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 12*0ea86f5aSGeert Uytterhoeven 13*0ea86f5aSGeert Uytterhoeven #include <dt-bindings/clock/renesas-cpg-mssr.h> 14*0ea86f5aSGeert Uytterhoeven 15*0ea86f5aSGeert Uytterhoeven /* r8a7794 CPG Core Clocks */ 16*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_Z2 0 17*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZG 1 18*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZTR 2 19*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZTRD2 3 20*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZT 4 21*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZX 5 22*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZS 6 23*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_HP 7 24*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_I 8 25*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_B 9 26*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_LB 10 27*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_P 11 28*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_CL 12 29*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_CP 13 30*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_M2 14 31*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ADSP 15 32*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZB3 16 33*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZB3D2 17 34*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_DDR 18 35*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SDH 19 36*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SD0 20 37*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SD2 21 38*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SD3 22 39*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_MMC0 23 40*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_MP 24 41*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_QSPI 25 42*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_CPEX 26 43*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_RCAN 27 44*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_R 28 45*0ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_OSC 29 46*0ea86f5aSGeert Uytterhoeven 47*0ea86f5aSGeert Uytterhoeven #endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ 48