1*34806f12SGeert Uytterhoeven /* 2*34806f12SGeert Uytterhoeven * Copyright (C) 2015 Renesas Electronics Corp. 3*34806f12SGeert Uytterhoeven * 4*34806f12SGeert Uytterhoeven * This program is free software; you can redistribute it and/or modify 5*34806f12SGeert Uytterhoeven * it under the terms of the GNU General Public License as published by 6*34806f12SGeert Uytterhoeven * the Free Software Foundation; either version 2 of the License, or 7*34806f12SGeert Uytterhoeven * (at your option) any later version. 8*34806f12SGeert Uytterhoeven */ 9*34806f12SGeert Uytterhoeven 10*34806f12SGeert Uytterhoeven #ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 11*34806f12SGeert Uytterhoeven #define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 12*34806f12SGeert Uytterhoeven 13*34806f12SGeert Uytterhoeven #include <dt-bindings/clock/renesas-cpg-mssr.h> 14*34806f12SGeert Uytterhoeven 15*34806f12SGeert Uytterhoeven /* r8a7792 CPG Core Clocks */ 16*34806f12SGeert Uytterhoeven #define R8A7792_CLK_Z 0 17*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZG 1 18*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZTR 2 19*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZTRD2 3 20*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZT 4 21*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZX 5 22*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZS 6 23*34806f12SGeert Uytterhoeven #define R8A7792_CLK_HP 7 24*34806f12SGeert Uytterhoeven #define R8A7792_CLK_I 8 25*34806f12SGeert Uytterhoeven #define R8A7792_CLK_B 9 26*34806f12SGeert Uytterhoeven #define R8A7792_CLK_LB 10 27*34806f12SGeert Uytterhoeven #define R8A7792_CLK_P 11 28*34806f12SGeert Uytterhoeven #define R8A7792_CLK_CL 12 29*34806f12SGeert Uytterhoeven #define R8A7792_CLK_M2 13 30*34806f12SGeert Uytterhoeven #define R8A7792_CLK_IMP 14 31*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZB3 15 32*34806f12SGeert Uytterhoeven #define R8A7792_CLK_ZB3D2 16 33*34806f12SGeert Uytterhoeven #define R8A7792_CLK_DDR 17 34*34806f12SGeert Uytterhoeven #define R8A7792_CLK_SD 18 35*34806f12SGeert Uytterhoeven #define R8A7792_CLK_MP 19 36*34806f12SGeert Uytterhoeven #define R8A7792_CLK_QSPI 20 37*34806f12SGeert Uytterhoeven #define R8A7792_CLK_CP 21 38*34806f12SGeert Uytterhoeven #define R8A7792_CLK_CPEX 22 39*34806f12SGeert Uytterhoeven #define R8A7792_CLK_RCAN 23 40*34806f12SGeert Uytterhoeven #define R8A7792_CLK_R 24 41*34806f12SGeert Uytterhoeven #define R8A7792_CLK_OSC 25 42*34806f12SGeert Uytterhoeven 43*34806f12SGeert Uytterhoeven #endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ 44