162f32ddeSBiju Das /* SPDX-License-Identifier: GPL-2.0 262f32ddeSBiju Das * 362f32ddeSBiju Das * Copyright (C) 2018 Renesas Electronics Corp. 462f32ddeSBiju Das */ 562f32ddeSBiju Das #ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ 662f32ddeSBiju Das #define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ 762f32ddeSBiju Das 862f32ddeSBiju Das #include <dt-bindings/clock/renesas-cpg-mssr.h> 962f32ddeSBiju Das 1062f32ddeSBiju Das /* r8a774a1 CPG Core Clocks */ 1162f32ddeSBiju Das #define R8A774A1_CLK_Z 0 1262f32ddeSBiju Das #define R8A774A1_CLK_Z2 1 1362f32ddeSBiju Das #define R8A774A1_CLK_ZG 2 1462f32ddeSBiju Das #define R8A774A1_CLK_ZTR 3 1562f32ddeSBiju Das #define R8A774A1_CLK_ZTRD2 4 1662f32ddeSBiju Das #define R8A774A1_CLK_ZT 5 1762f32ddeSBiju Das #define R8A774A1_CLK_ZX 6 1862f32ddeSBiju Das #define R8A774A1_CLK_S0D1 7 1962f32ddeSBiju Das #define R8A774A1_CLK_S0D2 8 2062f32ddeSBiju Das #define R8A774A1_CLK_S0D3 9 2162f32ddeSBiju Das #define R8A774A1_CLK_S0D4 10 2262f32ddeSBiju Das #define R8A774A1_CLK_S0D6 11 2362f32ddeSBiju Das #define R8A774A1_CLK_S0D8 12 2462f32ddeSBiju Das #define R8A774A1_CLK_S0D12 13 2562f32ddeSBiju Das #define R8A774A1_CLK_S1D2 14 2662f32ddeSBiju Das #define R8A774A1_CLK_S1D4 15 2762f32ddeSBiju Das #define R8A774A1_CLK_S2D1 16 2862f32ddeSBiju Das #define R8A774A1_CLK_S2D2 17 2962f32ddeSBiju Das #define R8A774A1_CLK_S2D4 18 3062f32ddeSBiju Das #define R8A774A1_CLK_S3D1 19 3162f32ddeSBiju Das #define R8A774A1_CLK_S3D2 20 3262f32ddeSBiju Das #define R8A774A1_CLK_S3D4 21 3362f32ddeSBiju Das #define R8A774A1_CLK_LB 22 3462f32ddeSBiju Das #define R8A774A1_CLK_CL 23 3562f32ddeSBiju Das #define R8A774A1_CLK_ZB3 24 3662f32ddeSBiju Das #define R8A774A1_CLK_ZB3D2 25 3762f32ddeSBiju Das #define R8A774A1_CLK_ZB3D4 26 3862f32ddeSBiju Das #define R8A774A1_CLK_CR 27 3962f32ddeSBiju Das #define R8A774A1_CLK_CRD2 28 4062f32ddeSBiju Das #define R8A774A1_CLK_SD0H 29 4162f32ddeSBiju Das #define R8A774A1_CLK_SD0 30 4262f32ddeSBiju Das #define R8A774A1_CLK_SD1H 31 4362f32ddeSBiju Das #define R8A774A1_CLK_SD1 32 4462f32ddeSBiju Das #define R8A774A1_CLK_SD2H 33 4562f32ddeSBiju Das #define R8A774A1_CLK_SD2 34 4662f32ddeSBiju Das #define R8A774A1_CLK_SD3H 35 4762f32ddeSBiju Das #define R8A774A1_CLK_SD3 36 4862f32ddeSBiju Das #define R8A774A1_CLK_RPC 37 4962f32ddeSBiju Das #define R8A774A1_CLK_RPCD2 38 5062f32ddeSBiju Das #define R8A774A1_CLK_MSO 39 5162f32ddeSBiju Das #define R8A774A1_CLK_HDMI 40 5262f32ddeSBiju Das #define R8A774A1_CLK_CSI0 41 5362f32ddeSBiju Das #define R8A774A1_CLK_CP 42 5462f32ddeSBiju Das #define R8A774A1_CLK_CPEX 43 5562f32ddeSBiju Das #define R8A774A1_CLK_R 44 5662f32ddeSBiju Das #define R8A774A1_CLK_OSC 45 57*9d034e15SFabrizio Castro #define R8A774A1_CLK_CANFD 46 5862f32ddeSBiju Das 5962f32ddeSBiju Das #endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ 60