1*6ff9cb53SBiju Das /* SPDX-License-Identifier: GPL-2.0 2*6ff9cb53SBiju Das * 3*6ff9cb53SBiju Das * Copyright (C) 2018 Renesas Electronics Corp. 4*6ff9cb53SBiju Das */ 5*6ff9cb53SBiju Das #ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ 6*6ff9cb53SBiju Das #define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ 7*6ff9cb53SBiju Das 8*6ff9cb53SBiju Das #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*6ff9cb53SBiju Das 10*6ff9cb53SBiju Das /* r8a7744 CPG Core Clocks */ 11*6ff9cb53SBiju Das #define R8A7744_CLK_Z 0 12*6ff9cb53SBiju Das #define R8A7744_CLK_ZG 1 13*6ff9cb53SBiju Das #define R8A7744_CLK_ZTR 2 14*6ff9cb53SBiju Das #define R8A7744_CLK_ZTRD2 3 15*6ff9cb53SBiju Das #define R8A7744_CLK_ZT 4 16*6ff9cb53SBiju Das #define R8A7744_CLK_ZX 5 17*6ff9cb53SBiju Das #define R8A7744_CLK_ZS 6 18*6ff9cb53SBiju Das #define R8A7744_CLK_HP 7 19*6ff9cb53SBiju Das #define R8A7744_CLK_B 9 20*6ff9cb53SBiju Das #define R8A7744_CLK_LB 10 21*6ff9cb53SBiju Das #define R8A7744_CLK_P 11 22*6ff9cb53SBiju Das #define R8A7744_CLK_CL 12 23*6ff9cb53SBiju Das #define R8A7744_CLK_M2 13 24*6ff9cb53SBiju Das #define R8A7744_CLK_ZB3 15 25*6ff9cb53SBiju Das #define R8A7744_CLK_ZB3D2 16 26*6ff9cb53SBiju Das #define R8A7744_CLK_DDR 17 27*6ff9cb53SBiju Das #define R8A7744_CLK_SDH 18 28*6ff9cb53SBiju Das #define R8A7744_CLK_SD0 19 29*6ff9cb53SBiju Das #define R8A7744_CLK_SD2 20 30*6ff9cb53SBiju Das #define R8A7744_CLK_SD3 21 31*6ff9cb53SBiju Das #define R8A7744_CLK_MMC0 22 32*6ff9cb53SBiju Das #define R8A7744_CLK_MP 23 33*6ff9cb53SBiju Das #define R8A7744_CLK_QSPI 26 34*6ff9cb53SBiju Das #define R8A7744_CLK_CP 27 35*6ff9cb53SBiju Das #define R8A7744_CLK_RCAN 28 36*6ff9cb53SBiju Das #define R8A7744_CLK_R 29 37*6ff9cb53SBiju Das #define R8A7744_CLK_OSC 30 38*6ff9cb53SBiju Das 39*6ff9cb53SBiju Das #endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */ 40