1*4e195933SSergei Shtylyov /* 2*4e195933SSergei Shtylyov * Copyright (C) 2016 Cogent Embedded Inc. 3*4e195933SSergei Shtylyov * 4*4e195933SSergei Shtylyov * This program is free software; you can redistribute it and/or modify 5*4e195933SSergei Shtylyov * it under the terms of the GNU General Public License as published by 6*4e195933SSergei Shtylyov * the Free Software Foundation; either version 2 of the License, or 7*4e195933SSergei Shtylyov * (at your option) any later version. 8*4e195933SSergei Shtylyov */ 9*4e195933SSergei Shtylyov #ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ 10*4e195933SSergei Shtylyov #define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ 11*4e195933SSergei Shtylyov 12*4e195933SSergei Shtylyov #include <dt-bindings/clock/renesas-cpg-mssr.h> 13*4e195933SSergei Shtylyov 14*4e195933SSergei Shtylyov /* r8a7743 CPG Core Clocks */ 15*4e195933SSergei Shtylyov #define R8A7743_CLK_Z 0 16*4e195933SSergei Shtylyov #define R8A7743_CLK_ZG 1 17*4e195933SSergei Shtylyov #define R8A7743_CLK_ZTR 2 18*4e195933SSergei Shtylyov #define R8A7743_CLK_ZTRD2 3 19*4e195933SSergei Shtylyov #define R8A7743_CLK_ZT 4 20*4e195933SSergei Shtylyov #define R8A7743_CLK_ZX 5 21*4e195933SSergei Shtylyov #define R8A7743_CLK_ZS 6 22*4e195933SSergei Shtylyov #define R8A7743_CLK_HP 7 23*4e195933SSergei Shtylyov #define R8A7743_CLK_B 9 24*4e195933SSergei Shtylyov #define R8A7743_CLK_LB 10 25*4e195933SSergei Shtylyov #define R8A7743_CLK_P 11 26*4e195933SSergei Shtylyov #define R8A7743_CLK_CL 12 27*4e195933SSergei Shtylyov #define R8A7743_CLK_M2 13 28*4e195933SSergei Shtylyov #define R8A7743_CLK_ZB3 15 29*4e195933SSergei Shtylyov #define R8A7743_CLK_ZB3D2 16 30*4e195933SSergei Shtylyov #define R8A7743_CLK_DDR 17 31*4e195933SSergei Shtylyov #define R8A7743_CLK_SDH 18 32*4e195933SSergei Shtylyov #define R8A7743_CLK_SD0 19 33*4e195933SSergei Shtylyov #define R8A7743_CLK_SD2 20 34*4e195933SSergei Shtylyov #define R8A7743_CLK_SD3 21 35*4e195933SSergei Shtylyov #define R8A7743_CLK_MMC0 22 36*4e195933SSergei Shtylyov #define R8A7743_CLK_MP 23 37*4e195933SSergei Shtylyov #define R8A7743_CLK_QSPI 26 38*4e195933SSergei Shtylyov #define R8A7743_CLK_CP 27 39*4e195933SSergei Shtylyov #define R8A7743_CLK_RCAN 28 40*4e195933SSergei Shtylyov #define R8A7743_CLK_R 29 41*4e195933SSergei Shtylyov #define R8A7743_CLK_OSC 30 42*4e195933SSergei Shtylyov 43*4e195933SSergei Shtylyov #endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */ 44