1*41b2df22SLad Prabhakar /* SPDX-License-Identifier: GPL-2.0+ 2*41b2df22SLad Prabhakar * 3*41b2df22SLad Prabhakar * Copyright (C) 2020 Renesas Electronics Corp. 4*41b2df22SLad Prabhakar */ 5*41b2df22SLad Prabhakar #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ 6*41b2df22SLad Prabhakar #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ 7*41b2df22SLad Prabhakar 8*41b2df22SLad Prabhakar #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*41b2df22SLad Prabhakar 10*41b2df22SLad Prabhakar /* r8a7742 CPG Core Clocks */ 11*41b2df22SLad Prabhakar #define R8A7742_CLK_Z 0 12*41b2df22SLad Prabhakar #define R8A7742_CLK_Z2 1 13*41b2df22SLad Prabhakar #define R8A7742_CLK_ZG 2 14*41b2df22SLad Prabhakar #define R8A7742_CLK_ZTR 3 15*41b2df22SLad Prabhakar #define R8A7742_CLK_ZTRD2 4 16*41b2df22SLad Prabhakar #define R8A7742_CLK_ZT 5 17*41b2df22SLad Prabhakar #define R8A7742_CLK_ZX 6 18*41b2df22SLad Prabhakar #define R8A7742_CLK_ZS 7 19*41b2df22SLad Prabhakar #define R8A7742_CLK_HP 8 20*41b2df22SLad Prabhakar #define R8A7742_CLK_B 9 21*41b2df22SLad Prabhakar #define R8A7742_CLK_LB 10 22*41b2df22SLad Prabhakar #define R8A7742_CLK_P 11 23*41b2df22SLad Prabhakar #define R8A7742_CLK_CL 12 24*41b2df22SLad Prabhakar #define R8A7742_CLK_M2 13 25*41b2df22SLad Prabhakar #define R8A7742_CLK_ZB3 14 26*41b2df22SLad Prabhakar #define R8A7742_CLK_ZB3D2 15 27*41b2df22SLad Prabhakar #define R8A7742_CLK_DDR 16 28*41b2df22SLad Prabhakar #define R8A7742_CLK_SDH 17 29*41b2df22SLad Prabhakar #define R8A7742_CLK_SD0 18 30*41b2df22SLad Prabhakar #define R8A7742_CLK_SD1 19 31*41b2df22SLad Prabhakar #define R8A7742_CLK_SD2 20 32*41b2df22SLad Prabhakar #define R8A7742_CLK_SD3 21 33*41b2df22SLad Prabhakar #define R8A7742_CLK_MMC0 22 34*41b2df22SLad Prabhakar #define R8A7742_CLK_MMC1 23 35*41b2df22SLad Prabhakar #define R8A7742_CLK_MP 24 36*41b2df22SLad Prabhakar #define R8A7742_CLK_QSPI 25 37*41b2df22SLad Prabhakar #define R8A7742_CLK_CP 26 38*41b2df22SLad Prabhakar #define R8A7742_CLK_RCAN 27 39*41b2df22SLad Prabhakar #define R8A7742_CLK_R 28 40*41b2df22SLad Prabhakar #define R8A7742_CLK_OSC 29 41*41b2df22SLad Prabhakar 42*41b2df22SLad Prabhakar #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */ 43