1*8b1750eaSTaniya Das /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*8b1750eaSTaniya Das /* 3*8b1750eaSTaniya Das * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4*8b1750eaSTaniya Das */ 5*8b1750eaSTaniya Das 6*8b1750eaSTaniya Das #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H 7*8b1750eaSTaniya Das #define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H 8*8b1750eaSTaniya Das 9*8b1750eaSTaniya Das /* DISP_CC clocks */ 10*8b1750eaSTaniya Das #define DISP_CC_MDSS_AHB_CLK 0 11*8b1750eaSTaniya Das #define DISP_CC_MDSS_AHB_CLK_SRC 1 12*8b1750eaSTaniya Das #define DISP_CC_MDSS_BYTE0_CLK 2 13*8b1750eaSTaniya Das #define DISP_CC_MDSS_BYTE0_CLK_SRC 3 14*8b1750eaSTaniya Das #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 15*8b1750eaSTaniya Das #define DISP_CC_MDSS_BYTE0_INTF_CLK 5 16*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_AUX_CLK 6 17*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_AUX_CLK_SRC 7 18*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_CRYPTO_CLK 8 19*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9 20*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_LINK_CLK 10 21*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_LINK_CLK_SRC 11 22*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 12 23*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_LINK_INTF_CLK 13 24*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_PIXEL1_CLK 14 25*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 15 26*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_PIXEL_CLK 16 27*8b1750eaSTaniya Das #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17 28*8b1750eaSTaniya Das #define DISP_CC_MDSS_ESC0_CLK 18 29*8b1750eaSTaniya Das #define DISP_CC_MDSS_ESC0_CLK_SRC 19 30*8b1750eaSTaniya Das #define DISP_CC_MDSS_MDP_CLK 20 31*8b1750eaSTaniya Das #define DISP_CC_MDSS_MDP_CLK_SRC 21 32*8b1750eaSTaniya Das #define DISP_CC_MDSS_MDP_LUT_CLK 22 33*8b1750eaSTaniya Das #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23 34*8b1750eaSTaniya Das #define DISP_CC_MDSS_PCLK0_CLK 24 35*8b1750eaSTaniya Das #define DISP_CC_MDSS_PCLK0_CLK_SRC 25 36*8b1750eaSTaniya Das #define DISP_CC_MDSS_ROT_CLK 26 37*8b1750eaSTaniya Das #define DISP_CC_MDSS_ROT_CLK_SRC 27 38*8b1750eaSTaniya Das #define DISP_CC_MDSS_RSCC_AHB_CLK 28 39*8b1750eaSTaniya Das #define DISP_CC_MDSS_RSCC_VSYNC_CLK 29 40*8b1750eaSTaniya Das #define DISP_CC_MDSS_VSYNC_CLK 30 41*8b1750eaSTaniya Das #define DISP_CC_MDSS_VSYNC_CLK_SRC 31 42*8b1750eaSTaniya Das #define DISP_CC_PLL0 32 43*8b1750eaSTaniya Das #define DISP_CC_XO_CLK 33 44*8b1750eaSTaniya Das 45*8b1750eaSTaniya Das /* DISP_CC power domains */ 46*8b1750eaSTaniya Das #define MDSS_CORE_GDSC 0 47*8b1750eaSTaniya Das 48*8b1750eaSTaniya Das /* DISP_CC resets */ 49*8b1750eaSTaniya Das #define DISP_CC_MDSS_CORE_BCR 0 50*8b1750eaSTaniya Das #define DISP_CC_MDSS_RSCC_BCR 1 51*8b1750eaSTaniya Das 52*8b1750eaSTaniya Das #endif 53