xref: /linux/include/dt-bindings/clock/qcom,mmcc-msm8974.h (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732)
1 /*
2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H
15 #define _DT_BINDINGS_CLK_MSM_MMCC_8974_H
16 
17 #define MMSS_AHB_CLK_SRC				0
18 #define MMSS_AXI_CLK_SRC				1
19 #define MMPLL0						2
20 #define MMPLL0_VOTE					3
21 #define MMPLL1						4
22 #define MMPLL1_VOTE					5
23 #define MMPLL2						6
24 #define MMPLL3						7
25 #define CSI0_CLK_SRC					8
26 #define CSI1_CLK_SRC					9
27 #define CSI2_CLK_SRC					10
28 #define CSI3_CLK_SRC					11
29 #define VFE0_CLK_SRC					12
30 #define VFE1_CLK_SRC					13
31 #define MDP_CLK_SRC					14
32 #define GFX3D_CLK_SRC					15
33 #define JPEG0_CLK_SRC					16
34 #define JPEG1_CLK_SRC					17
35 #define JPEG2_CLK_SRC					18
36 #define PCLK0_CLK_SRC					19
37 #define PCLK1_CLK_SRC					20
38 #define VCODEC0_CLK_SRC					21
39 #define CCI_CLK_SRC					22
40 #define CAMSS_GP0_CLK_SRC				23
41 #define CAMSS_GP1_CLK_SRC				24
42 #define MCLK0_CLK_SRC					25
43 #define MCLK1_CLK_SRC					26
44 #define MCLK2_CLK_SRC					27
45 #define MCLK3_CLK_SRC					28
46 #define CSI0PHYTIMER_CLK_SRC				29
47 #define CSI1PHYTIMER_CLK_SRC				30
48 #define CSI2PHYTIMER_CLK_SRC				31
49 #define CPP_CLK_SRC					32
50 #define BYTE0_CLK_SRC					33
51 #define BYTE1_CLK_SRC					34
52 #define EDPAUX_CLK_SRC					35
53 #define EDPLINK_CLK_SRC					36
54 #define EDPPIXEL_CLK_SRC				37
55 #define ESC0_CLK_SRC					38
56 #define ESC1_CLK_SRC					39
57 #define EXTPCLK_CLK_SRC					40
58 #define HDMI_CLK_SRC					41
59 #define VSYNC_CLK_SRC					42
60 #define MMSS_RBCPR_CLK_SRC				43
61 #define CAMSS_CCI_CCI_AHB_CLK				44
62 #define CAMSS_CCI_CCI_CLK				45
63 #define CAMSS_CSI0_AHB_CLK				46
64 #define CAMSS_CSI0_CLK					47
65 #define CAMSS_CSI0PHY_CLK				48
66 #define CAMSS_CSI0PIX_CLK				49
67 #define CAMSS_CSI0RDI_CLK				50
68 #define CAMSS_CSI1_AHB_CLK				51
69 #define CAMSS_CSI1_CLK					52
70 #define CAMSS_CSI1PHY_CLK				53
71 #define CAMSS_CSI1PIX_CLK				54
72 #define CAMSS_CSI1RDI_CLK				55
73 #define CAMSS_CSI2_AHB_CLK				56
74 #define CAMSS_CSI2_CLK					57
75 #define CAMSS_CSI2PHY_CLK				58
76 #define CAMSS_CSI2PIX_CLK				59
77 #define CAMSS_CSI2RDI_CLK				60
78 #define CAMSS_CSI3_AHB_CLK				61
79 #define CAMSS_CSI3_CLK					62
80 #define CAMSS_CSI3PHY_CLK				63
81 #define CAMSS_CSI3PIX_CLK				64
82 #define CAMSS_CSI3RDI_CLK				65
83 #define CAMSS_CSI_VFE0_CLK				66
84 #define CAMSS_CSI_VFE1_CLK				67
85 #define CAMSS_GP0_CLK					68
86 #define CAMSS_GP1_CLK					69
87 #define CAMSS_ISPIF_AHB_CLK				70
88 #define CAMSS_JPEG_JPEG0_CLK				71
89 #define CAMSS_JPEG_JPEG1_CLK				72
90 #define CAMSS_JPEG_JPEG2_CLK				73
91 #define CAMSS_JPEG_JPEG_AHB_CLK				74
92 #define CAMSS_JPEG_JPEG_AXI_CLK				75
93 #define CAMSS_JPEG_JPEG_OCMEMNOC_CLK			76
94 #define CAMSS_MCLK0_CLK					77
95 #define CAMSS_MCLK1_CLK					78
96 #define CAMSS_MCLK2_CLK					79
97 #define CAMSS_MCLK3_CLK					80
98 #define CAMSS_MICRO_AHB_CLK				81
99 #define CAMSS_PHY0_CSI0PHYTIMER_CLK			82
100 #define CAMSS_PHY1_CSI1PHYTIMER_CLK			83
101 #define CAMSS_PHY2_CSI2PHYTIMER_CLK			84
102 #define CAMSS_TOP_AHB_CLK				85
103 #define CAMSS_VFE_CPP_AHB_CLK				86
104 #define CAMSS_VFE_CPP_CLK				87
105 #define CAMSS_VFE_VFE0_CLK				88
106 #define CAMSS_VFE_VFE1_CLK				89
107 #define CAMSS_VFE_VFE_AHB_CLK				90
108 #define CAMSS_VFE_VFE_AXI_CLK				91
109 #define CAMSS_VFE_VFE_OCMEMNOC_CLK			92
110 #define MDSS_AHB_CLK					93
111 #define MDSS_AXI_CLK					94
112 #define MDSS_BYTE0_CLK					95
113 #define MDSS_BYTE1_CLK					96
114 #define MDSS_EDPAUX_CLK					97
115 #define MDSS_EDPLINK_CLK				98
116 #define MDSS_EDPPIXEL_CLK				99
117 #define MDSS_ESC0_CLK					100
118 #define MDSS_ESC1_CLK					101
119 #define MDSS_EXTPCLK_CLK				102
120 #define MDSS_HDMI_AHB_CLK				103
121 #define MDSS_HDMI_CLK					104
122 #define MDSS_MDP_CLK					105
123 #define MDSS_MDP_LUT_CLK				106
124 #define MDSS_PCLK0_CLK					107
125 #define MDSS_PCLK1_CLK					108
126 #define MDSS_VSYNC_CLK					109
127 #define MMSS_MISC_AHB_CLK				110
128 #define MMSS_MMSSNOC_AHB_CLK				111
129 #define MMSS_MMSSNOC_BTO_AHB_CLK			112
130 #define MMSS_MMSSNOC_AXI_CLK				113
131 #define MMSS_S0_AXI_CLK					114
132 #define OCMEMCX_AHB_CLK					115
133 #define OCMEMCX_OCMEMNOC_CLK				116
134 #define OXILI_OCMEMGX_CLK				117
135 #define OCMEMNOC_CLK					118
136 #define OXILI_GFX3D_CLK					119
137 #define OXILICX_AHB_CLK					120
138 #define OXILICX_AXI_CLK					121
139 #define VENUS0_AHB_CLK					122
140 #define VENUS0_AXI_CLK					123
141 #define VENUS0_OCMEMNOC_CLK				124
142 #define VENUS0_VCODEC0_CLK				125
143 #define OCMEMNOC_CLK_SRC				126
144 #define SPDM_JPEG0					127
145 #define SPDM_JPEG1					128
146 #define SPDM_MDP					129
147 #define SPDM_AXI					130
148 #define SPDM_VCODEC0					131
149 #define SPDM_VFE0					132
150 #define SPDM_VFE1					133
151 #define SPDM_JPEG2					134
152 #define SPDM_PCLK1					135
153 #define SPDM_GFX3D					136
154 #define SPDM_AHB					137
155 #define SPDM_PCLK0					138
156 #define SPDM_OCMEMNOC					139
157 #define SPDM_CSI0					140
158 #define SPDM_RM_AXI					141
159 #define SPDM_RM_OCMEMNOC				142
160 
161 #endif
162