1*f92b7782SKathiravan Thirumoorthy /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*f92b7782SKathiravan Thirumoorthy /* 3*f92b7782SKathiravan Thirumoorthy * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*f92b7782SKathiravan Thirumoorthy */ 5*f92b7782SKathiravan Thirumoorthy 6*f92b7782SKathiravan Thirumoorthy #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H 7*f92b7782SKathiravan Thirumoorthy #define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H 8*f92b7782SKathiravan Thirumoorthy 9*f92b7782SKathiravan Thirumoorthy #define GCC_ADSS_PWM_CLK 0 10*f92b7782SKathiravan Thirumoorthy #define GCC_ADSS_PWM_CLK_SRC 1 11*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE0_1LANE_M_CLK 2 12*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE0_1LANE_S_CLK 3 13*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE1_2LANE_M_CLK 4 14*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE1_2LANE_S_CLK 5 15*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE2_2LANE_M_CLK 6 16*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE2_2LANE_S_CLK 7 17*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE3_2LANE_M_CLK 8 18*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE3_2LANE_S_CLK 9 19*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE4_1LANE_M_CLK 10 20*f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE4_1LANE_S_CLK 11 21*f92b7782SKathiravan Thirumoorthy #define GCC_CMN_12GPLL_AHB_CLK 12 22*f92b7782SKathiravan Thirumoorthy #define GCC_CMN_12GPLL_APU_CLK 13 23*f92b7782SKathiravan Thirumoorthy #define GCC_CMN_12GPLL_SYS_CLK 14 24*f92b7782SKathiravan Thirumoorthy #define GCC_CMN_LDO_CLK 15 25*f92b7782SKathiravan Thirumoorthy #define GCC_MDIO_AHB_CLK 16 26*f92b7782SKathiravan Thirumoorthy #define GCC_NSSCC_CLK 17 27*f92b7782SKathiravan Thirumoorthy #define GCC_NSSCFG_CLK 18 28*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_ATB_CLK 19 29*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_1_CLK 20 30*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 31*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_CLK 22 32*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 33*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_NSSCC_CLK 24 34*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_PCNOC_1_CLK 25 35*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_QOSGEN_REF_CLK 26 36*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_SNOC_1_CLK 27 37*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_SNOC_CLK 28 38*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_TIMEOUT_REF_CLK 29 39*f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_XO_DCD_CLK 30 40*f92b7782SKathiravan Thirumoorthy #define GCC_NSS_TS_CLK 31 41*f92b7782SKathiravan Thirumoorthy #define GCC_NSS_TS_CLK_SRC 32 42*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AHB_CLK 33 43*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AUX_CLK 34 44*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_M_CLK 35 45*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_M_CLK_SRC 36 46*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_BRIDGE_CLK 37 47*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_CLK 38 48*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_CLK_SRC 39 49*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_PIPE_CLK 40 50*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_PIPE_CLK_SRC 41 51*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_RCHNG_CLK 42 52*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_RCHNG_CLK_SRC 43 53*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AHB_CLK 44 54*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AUX_CLK 45 55*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_M_CLK 46 56*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_M_CLK_SRC 47 57*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_BRIDGE_CLK 48 58*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_CLK 49 59*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_CLK_SRC 50 60*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_PIPE_CLK 51 61*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_PIPE_CLK_SRC 52 62*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_RCHNG_CLK 53 63*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_RCHNG_CLK_SRC 54 64*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AHB_CLK 55 65*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AUX_CLK 56 66*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_M_CLK 57 67*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_M_CLK_SRC 58 68*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_S_BRIDGE_CLK 59 69*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_S_CLK 60 70*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_S_CLK_SRC 61 71*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_PIPE_CLK 62 72*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_PIPE_CLK_SRC 63 73*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_RCHNG_CLK 64 74*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_RCHNG_CLK_SRC 65 75*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AHB_CLK 66 76*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AUX_CLK 67 77*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_M_CLK 68 78*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_M_CLK_SRC 69 79*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_S_BRIDGE_CLK 70 80*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_S_CLK 71 81*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_S_CLK_SRC 72 82*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_PIPE_CLK 73 83*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_PIPE_CLK_SRC 74 84*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_RCHNG_CLK 75 85*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_RCHNG_CLK_SRC 76 86*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AHB_CLK 77 87*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AUX_CLK 78 88*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_M_CLK 79 89*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_M_CLK_SRC 80 90*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_S_BRIDGE_CLK 81 91*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_S_CLK 82 92*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_S_CLK_SRC 83 93*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_PIPE_CLK 84 94*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_PIPE_CLK_SRC 85 95*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_RCHNG_CLK 86 96*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_RCHNG_CLK_SRC 87 97*f92b7782SKathiravan Thirumoorthy #define GCC_PCIE_AUX_CLK_SRC 88 98*f92b7782SKathiravan Thirumoorthy #define GCC_PCNOC_BFDCD_CLK_SRC 89 99*f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_AT_CLK 90 100*f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_AT_CLK_SRC 91 101*f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_DAP_CLK 92 102*f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_TSCTR_CLK_SRC 93 103*f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_AHB_CLK 94 104*f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_CLK 95 105*f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_CLK_SRC 96 106*f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_IO_MACRO_CLK 97 107*f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_IO_MACRO_CLK_SRC 98 108*f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_SLEEP_CLK 99 109*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_2X_CORE_CLK 100 110*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_2X_CORE_CLK_SRC 101 111*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_AHB_MST_CLK 102 112*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_AHB_SLV_CLK 103 113*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_CORE_CLK 104 114*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_SLEEP_CLK 105 115*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE0_CLK 106 116*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE0_CLK_SRC 107 117*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE1_CLK 108 118*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE1_CLK_SRC 109 119*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE2_CLK 110 120*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE2_CLK_SRC 111 121*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE3_CLK 112 122*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE3_CLK_SRC 113 123*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE4_CLK 114 124*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE4_CLK_SRC 115 125*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE5_CLK 116 126*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE5_CLK_SRC 117 127*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE6_CLK 118 128*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE6_CLK_SRC 119 129*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE7_CLK 120 130*f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE7_CLK_SRC 121 131*f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_AHB_CLK 122 132*f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_APPS_CLK 123 133*f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_APPS_CLK_SRC 124 134*f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_ICE_CORE_CLK 125 135*f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_ICE_CORE_CLK_SRC 126 136*f92b7782SKathiravan Thirumoorthy #define GCC_SLEEP_CLK_SRC 127 137*f92b7782SKathiravan Thirumoorthy #define GCC_SNOC_USB_CLK 128 138*f92b7782SKathiravan Thirumoorthy #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 139*f92b7782SKathiravan Thirumoorthy #define GCC_TLMM_AHB_CLK 130 140*f92b7782SKathiravan Thirumoorthy #define GCC_TLMM_CLK 131 141*f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY0_AHB_CLK 132 142*f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY0_SYS_CLK 133 143*f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY1_AHB_CLK 134 144*f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY1_SYS_CLK 135 145*f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY2_AHB_CLK 136 146*f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY2_SYS_CLK 137 147*f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY_SYS_CLK_SRC 138 148*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_AUX_CLK 139 149*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_AUX_CLK_SRC 140 150*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_EUD_AT_CLK 141 151*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MASTER_CLK 142 152*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MASTER_CLK_SRC 143 153*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_CLK 144 154*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_CLK_SRC 145 155*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 146 156*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_PHY_CFG_AHB_CLK 147 157*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_PIPE_CLK 148 158*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_PIPE_CLK_SRC 149 159*f92b7782SKathiravan Thirumoorthy #define GCC_USB0_SLEEP_CLK 150 160*f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MASTER_CLK 151 161*f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MOCK_UTMI_CLK 152 162*f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MOCK_UTMI_CLK_SRC 153 163*f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 154 164*f92b7782SKathiravan Thirumoorthy #define GCC_USB1_PHY_CFG_AHB_CLK 155 165*f92b7782SKathiravan Thirumoorthy #define GCC_USB1_SLEEP_CLK 156 166*f92b7782SKathiravan Thirumoorthy #define GCC_XO_CLK_SRC 157 167*f92b7782SKathiravan Thirumoorthy #define GPLL0 158 168*f92b7782SKathiravan Thirumoorthy #define GPLL0_MAIN 159 169*f92b7782SKathiravan Thirumoorthy #define GPLL2 160 170*f92b7782SKathiravan Thirumoorthy #define GPLL2_OUT_MAIN 161 171*f92b7782SKathiravan Thirumoorthy #define GPLL4 162 172*f92b7782SKathiravan Thirumoorthy #endif 173