1*7156c650SJohn Crispin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*7156c650SJohn Crispin /* 3*7156c650SJohn Crispin * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4*7156c650SJohn Crispin */ 5*7156c650SJohn Crispin 6*7156c650SJohn Crispin #ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H 7*7156c650SJohn Crispin #define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H 8*7156c650SJohn Crispin 9*7156c650SJohn Crispin /* CMN PLL core clock. */ 10*7156c650SJohn Crispin #define IPQ8074_CMN_PLL_CLK 0 11*7156c650SJohn Crispin 12*7156c650SJohn Crispin /* The output clocks from CMN PLL of IPQ8074. */ 13*7156c650SJohn Crispin #define IPQ8074_BIAS_PLL_CC_CLK 1 14*7156c650SJohn Crispin #define IPQ8074_BIAS_PLL_NSS_NOC_CLK 2 15*7156c650SJohn Crispin #endif 16