xref: /linux/include/dt-bindings/clock/qcom,ipq5424-nsscc.h (revision a34b0e4e21d6be3c3d620aa7f9dfbf0e9550c19e)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3  * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4  */
5 
6 #ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
7 #define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
8 
9 /* NSS_CC clocks */
10 #define NSS_CC_CE_APB_CLK					0
11 #define NSS_CC_CE_AXI_CLK					1
12 #define NSS_CC_CE_CLK_SRC					2
13 #define NSS_CC_CFG_CLK_SRC					3
14 #define NSS_CC_DEBUG_CLK					4
15 #define NSS_CC_EIP_BFDCD_CLK_SRC				5
16 #define NSS_CC_EIP_CLK						6
17 #define NSS_CC_NSS_CSR_CLK					7
18 #define NSS_CC_NSSNOC_CE_APB_CLK				8
19 #define NSS_CC_NSSNOC_CE_AXI_CLK				9
20 #define NSS_CC_NSSNOC_EIP_CLK					10
21 #define NSS_CC_NSSNOC_NSS_CSR_CLK				11
22 #define NSS_CC_NSSNOC_PPE_CFG_CLK				12
23 #define NSS_CC_NSSNOC_PPE_CLK					13
24 #define NSS_CC_PORT1_MAC_CLK					14
25 #define NSS_CC_PORT1_RX_CLK					15
26 #define NSS_CC_PORT1_RX_CLK_SRC					16
27 #define NSS_CC_PORT1_RX_DIV_CLK_SRC				17
28 #define NSS_CC_PORT1_TX_CLK					18
29 #define NSS_CC_PORT1_TX_CLK_SRC					19
30 #define NSS_CC_PORT1_TX_DIV_CLK_SRC				20
31 #define NSS_CC_PORT2_MAC_CLK					21
32 #define NSS_CC_PORT2_RX_CLK					22
33 #define NSS_CC_PORT2_RX_CLK_SRC					23
34 #define NSS_CC_PORT2_RX_DIV_CLK_SRC				24
35 #define NSS_CC_PORT2_TX_CLK					25
36 #define NSS_CC_PORT2_TX_CLK_SRC					26
37 #define NSS_CC_PORT2_TX_DIV_CLK_SRC				27
38 #define NSS_CC_PORT3_MAC_CLK					28
39 #define NSS_CC_PORT3_RX_CLK					29
40 #define NSS_CC_PORT3_RX_CLK_SRC					30
41 #define NSS_CC_PORT3_RX_DIV_CLK_SRC				31
42 #define NSS_CC_PORT3_TX_CLK					32
43 #define NSS_CC_PORT3_TX_CLK_SRC					33
44 #define NSS_CC_PORT3_TX_DIV_CLK_SRC				34
45 #define NSS_CC_PPE_CLK_SRC					35
46 #define NSS_CC_PPE_EDMA_CFG_CLK					36
47 #define NSS_CC_PPE_EDMA_CLK					37
48 #define NSS_CC_PPE_SWITCH_BTQ_CLK				38
49 #define NSS_CC_PPE_SWITCH_CFG_CLK				39
50 #define NSS_CC_PPE_SWITCH_CLK					40
51 #define NSS_CC_PPE_SWITCH_IPE_CLK				41
52 #define NSS_CC_UNIPHY_PORT1_RX_CLK				42
53 #define NSS_CC_UNIPHY_PORT1_TX_CLK				43
54 #define NSS_CC_UNIPHY_PORT2_RX_CLK				44
55 #define NSS_CC_UNIPHY_PORT2_TX_CLK				45
56 #define NSS_CC_UNIPHY_PORT3_RX_CLK				46
57 #define NSS_CC_UNIPHY_PORT3_TX_CLK				47
58 #define NSS_CC_XGMAC0_PTP_REF_CLK				48
59 #define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC			49
60 #define NSS_CC_XGMAC1_PTP_REF_CLK				50
61 #define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC			51
62 #define NSS_CC_XGMAC2_PTP_REF_CLK				52
63 #define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC			53
64 
65 #endif
66