1*06ac2566SLuo Jie /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*06ac2566SLuo Jie /* 3*06ac2566SLuo Jie * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*06ac2566SLuo Jie */ 5*06ac2566SLuo Jie 6*06ac2566SLuo Jie #ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H 7*06ac2566SLuo Jie #define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H 8*06ac2566SLuo Jie 9*06ac2566SLuo Jie /* NSS_CC clocks */ 10*06ac2566SLuo Jie #define NSS_CC_CE_APB_CLK 0 11*06ac2566SLuo Jie #define NSS_CC_CE_AXI_CLK 1 12*06ac2566SLuo Jie #define NSS_CC_CE_CLK_SRC 2 13*06ac2566SLuo Jie #define NSS_CC_CFG_CLK_SRC 3 14*06ac2566SLuo Jie #define NSS_CC_DEBUG_CLK 4 15*06ac2566SLuo Jie #define NSS_CC_EIP_BFDCD_CLK_SRC 5 16*06ac2566SLuo Jie #define NSS_CC_EIP_CLK 6 17*06ac2566SLuo Jie #define NSS_CC_NSS_CSR_CLK 7 18*06ac2566SLuo Jie #define NSS_CC_NSSNOC_CE_APB_CLK 8 19*06ac2566SLuo Jie #define NSS_CC_NSSNOC_CE_AXI_CLK 9 20*06ac2566SLuo Jie #define NSS_CC_NSSNOC_EIP_CLK 10 21*06ac2566SLuo Jie #define NSS_CC_NSSNOC_NSS_CSR_CLK 11 22*06ac2566SLuo Jie #define NSS_CC_NSSNOC_PPE_CFG_CLK 12 23*06ac2566SLuo Jie #define NSS_CC_NSSNOC_PPE_CLK 13 24*06ac2566SLuo Jie #define NSS_CC_PORT1_MAC_CLK 14 25*06ac2566SLuo Jie #define NSS_CC_PORT1_RX_CLK 15 26*06ac2566SLuo Jie #define NSS_CC_PORT1_RX_CLK_SRC 16 27*06ac2566SLuo Jie #define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 28*06ac2566SLuo Jie #define NSS_CC_PORT1_TX_CLK 18 29*06ac2566SLuo Jie #define NSS_CC_PORT1_TX_CLK_SRC 19 30*06ac2566SLuo Jie #define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 31*06ac2566SLuo Jie #define NSS_CC_PORT2_MAC_CLK 21 32*06ac2566SLuo Jie #define NSS_CC_PORT2_RX_CLK 22 33*06ac2566SLuo Jie #define NSS_CC_PORT2_RX_CLK_SRC 23 34*06ac2566SLuo Jie #define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 35*06ac2566SLuo Jie #define NSS_CC_PORT2_TX_CLK 25 36*06ac2566SLuo Jie #define NSS_CC_PORT2_TX_CLK_SRC 26 37*06ac2566SLuo Jie #define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 38*06ac2566SLuo Jie #define NSS_CC_PORT3_MAC_CLK 28 39*06ac2566SLuo Jie #define NSS_CC_PORT3_RX_CLK 29 40*06ac2566SLuo Jie #define NSS_CC_PORT3_RX_CLK_SRC 30 41*06ac2566SLuo Jie #define NSS_CC_PORT3_RX_DIV_CLK_SRC 31 42*06ac2566SLuo Jie #define NSS_CC_PORT3_TX_CLK 32 43*06ac2566SLuo Jie #define NSS_CC_PORT3_TX_CLK_SRC 33 44*06ac2566SLuo Jie #define NSS_CC_PORT3_TX_DIV_CLK_SRC 34 45*06ac2566SLuo Jie #define NSS_CC_PPE_CLK_SRC 35 46*06ac2566SLuo Jie #define NSS_CC_PPE_EDMA_CFG_CLK 36 47*06ac2566SLuo Jie #define NSS_CC_PPE_EDMA_CLK 37 48*06ac2566SLuo Jie #define NSS_CC_PPE_SWITCH_BTQ_CLK 38 49*06ac2566SLuo Jie #define NSS_CC_PPE_SWITCH_CFG_CLK 39 50*06ac2566SLuo Jie #define NSS_CC_PPE_SWITCH_CLK 40 51*06ac2566SLuo Jie #define NSS_CC_PPE_SWITCH_IPE_CLK 41 52*06ac2566SLuo Jie #define NSS_CC_UNIPHY_PORT1_RX_CLK 42 53*06ac2566SLuo Jie #define NSS_CC_UNIPHY_PORT1_TX_CLK 43 54*06ac2566SLuo Jie #define NSS_CC_UNIPHY_PORT2_RX_CLK 44 55*06ac2566SLuo Jie #define NSS_CC_UNIPHY_PORT2_TX_CLK 45 56*06ac2566SLuo Jie #define NSS_CC_UNIPHY_PORT3_RX_CLK 46 57*06ac2566SLuo Jie #define NSS_CC_UNIPHY_PORT3_TX_CLK 47 58*06ac2566SLuo Jie #define NSS_CC_XGMAC0_PTP_REF_CLK 48 59*06ac2566SLuo Jie #define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49 60*06ac2566SLuo Jie #define NSS_CC_XGMAC1_PTP_REF_CLK 50 61*06ac2566SLuo Jie #define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51 62*06ac2566SLuo Jie #define NSS_CC_XGMAC2_PTP_REF_CLK 52 63*06ac2566SLuo Jie #define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53 64*06ac2566SLuo Jie 65*06ac2566SLuo Jie #endif 66