1*0c25ae62SLuo Jie /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*0c25ae62SLuo Jie /* 3*0c25ae62SLuo Jie * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4*0c25ae62SLuo Jie */ 5*0c25ae62SLuo Jie 6*0c25ae62SLuo Jie #ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H 7*0c25ae62SLuo Jie #define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H 8*0c25ae62SLuo Jie 9*0c25ae62SLuo Jie /* CMN PLL core clock. */ 10*0c25ae62SLuo Jie #define IPQ5424_CMN_PLL_CLK 0 11*0c25ae62SLuo Jie 12*0c25ae62SLuo Jie /* The output clocks from CMN PLL of IPQ5424. */ 13*0c25ae62SLuo Jie #define IPQ5424_XO_24MHZ_CLK 1 14*0c25ae62SLuo Jie #define IPQ5424_SLEEP_32KHZ_CLK 2 15*0c25ae62SLuo Jie #define IPQ5424_PCS_31P25MHZ_CLK 3 16*0c25ae62SLuo Jie #define IPQ5424_NSS_300MHZ_CLK 4 17*0c25ae62SLuo Jie #define IPQ5424_PPE_375MHZ_CLK 5 18*0c25ae62SLuo Jie #define IPQ5424_ETH0_50MHZ_CLK 6 19*0c25ae62SLuo Jie #define IPQ5424_ETH1_50MHZ_CLK 7 20*0c25ae62SLuo Jie #define IPQ5424_ETH2_50MHZ_CLK 8 21*0c25ae62SLuo Jie #define IPQ5424_ETH_25MHZ_CLK 9 22*0c25ae62SLuo Jie #endif 23