1*314b903cSGeorge Moussalem /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*314b903cSGeorge Moussalem /* 3*314b903cSGeorge Moussalem * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4*314b903cSGeorge Moussalem */ 5*314b903cSGeorge Moussalem 6*314b903cSGeorge Moussalem #ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H 7*314b903cSGeorge Moussalem #define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H 8*314b903cSGeorge Moussalem 9*314b903cSGeorge Moussalem /* CMN PLL core clock. */ 10*314b903cSGeorge Moussalem #define IPQ5018_CMN_PLL_CLK 0 11*314b903cSGeorge Moussalem 12*314b903cSGeorge Moussalem /* The output clocks from CMN PLL of IPQ5018. */ 13*314b903cSGeorge Moussalem #define IPQ5018_XO_24MHZ_CLK 1 14*314b903cSGeorge Moussalem #define IPQ5018_SLEEP_32KHZ_CLK 2 15*314b903cSGeorge Moussalem #define IPQ5018_ETH_50MHZ_CLK 3 16*314b903cSGeorge Moussalem #endif 17