xref: /linux/include/dt-bindings/clock/qcom,gcc-msm8994.h (revision 96ac6d435100450f0565708d9b885ea2a7400e0a)
1 /*
2  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 
15 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
16 #define _DT_BINDINGS_CLK_MSM_GCC_8994_H
17 
18 #define GPLL0_EARLY				0
19 #define GPLL0					1
20 #define GPLL4_EARLY				2
21 #define GPLL4					3
22 #define UFS_AXI_CLK_SRC				4
23 #define USB30_MASTER_CLK_SRC			5
24 #define BLSP1_QUP1_I2C_APPS_CLK_SRC		6
25 #define BLSP1_QUP1_SPI_APPS_CLK_SRC		7
26 #define BLSP1_QUP2_I2C_APPS_CLK_SRC		8
27 #define BLSP1_QUP2_SPI_APPS_CLK_SRC		9
28 #define BLSP1_QUP3_I2C_APPS_CLK_SRC		10
29 #define BLSP1_QUP3_SPI_APPS_CLK_SRC		11
30 #define BLSP1_QUP4_I2C_APPS_CLK_SRC		12
31 #define BLSP1_QUP4_SPI_APPS_CLK_SRC		13
32 #define BLSP1_QUP5_I2C_APPS_CLK_SRC		14
33 #define BLSP1_QUP5_SPI_APPS_CLK_SRC		15
34 #define BLSP1_QUP6_I2C_APPS_CLK_SRC		16
35 #define BLSP1_QUP6_SPI_APPS_CLK_SRC		17
36 #define BLSP1_UART1_APPS_CLK_SRC		18
37 #define BLSP1_UART2_APPS_CLK_SRC		19
38 #define BLSP1_UART3_APPS_CLK_SRC		20
39 #define BLSP1_UART4_APPS_CLK_SRC		21
40 #define BLSP1_UART5_APPS_CLK_SRC		22
41 #define BLSP1_UART6_APPS_CLK_SRC		23
42 #define BLSP2_QUP1_I2C_APPS_CLK_SRC		24
43 #define BLSP2_QUP1_SPI_APPS_CLK_SRC		25
44 #define BLSP2_QUP2_I2C_APPS_CLK_SRC		26
45 #define BLSP2_QUP2_SPI_APPS_CLK_SRC		27
46 #define BLSP2_QUP3_I2C_APPS_CLK_SRC		28
47 #define BLSP2_QUP3_SPI_APPS_CLK_SRC		29
48 #define BLSP2_QUP4_I2C_APPS_CLK_SRC		30
49 #define BLSP2_QUP4_SPI_APPS_CLK_SRC		31
50 #define BLSP2_QUP5_I2C_APPS_CLK_SRC		32
51 #define BLSP2_QUP5_SPI_APPS_CLK_SRC		33
52 #define BLSP2_QUP6_I2C_APPS_CLK_SRC		34
53 #define BLSP2_QUP6_SPI_APPS_CLK_SRC		35
54 #define BLSP2_UART1_APPS_CLK_SRC		36
55 #define BLSP2_UART2_APPS_CLK_SRC		37
56 #define BLSP2_UART3_APPS_CLK_SRC		38
57 #define BLSP2_UART4_APPS_CLK_SRC		39
58 #define BLSP2_UART5_APPS_CLK_SRC		40
59 #define BLSP2_UART6_APPS_CLK_SRC		41
60 #define GP1_CLK_SRC				42
61 #define GP2_CLK_SRC				43
62 #define GP3_CLK_SRC				44
63 #define PCIE_0_AUX_CLK_SRC			45
64 #define PCIE_0_PIPE_CLK_SRC			46
65 #define PCIE_1_AUX_CLK_SRC			47
66 #define PCIE_1_PIPE_CLK_SRC			48
67 #define PDM2_CLK_SRC				49
68 #define SDCC1_APPS_CLK_SRC			50
69 #define SDCC2_APPS_CLK_SRC			51
70 #define SDCC3_APPS_CLK_SRC			52
71 #define SDCC4_APPS_CLK_SRC			53
72 #define TSIF_REF_CLK_SRC			54
73 #define USB30_MOCK_UTMI_CLK_SRC			55
74 #define USB3_PHY_AUX_CLK_SRC			56
75 #define USB_HS_SYSTEM_CLK_SRC			57
76 #define GCC_BLSP1_AHB_CLK			58
77 #define GCC_BLSP1_QUP1_I2C_APPS_CLK		59
78 #define GCC_BLSP1_QUP1_SPI_APPS_CLK		60
79 #define GCC_BLSP1_QUP2_I2C_APPS_CLK		61
80 #define GCC_BLSP1_QUP2_SPI_APPS_CLK		62
81 #define GCC_BLSP1_QUP3_I2C_APPS_CLK		63
82 #define GCC_BLSP1_QUP3_SPI_APPS_CLK		64
83 #define GCC_BLSP1_QUP4_I2C_APPS_CLK		65
84 #define GCC_BLSP1_QUP4_SPI_APPS_CLK		66
85 #define GCC_BLSP1_QUP5_I2C_APPS_CLK		67
86 #define GCC_BLSP1_QUP5_SPI_APPS_CLK		68
87 #define GCC_BLSP1_QUP6_I2C_APPS_CLK		69
88 #define GCC_BLSP1_QUP6_SPI_APPS_CLK		70
89 #define GCC_BLSP1_UART1_APPS_CLK		71
90 #define GCC_BLSP1_UART2_APPS_CLK		72
91 #define GCC_BLSP1_UART3_APPS_CLK		73
92 #define GCC_BLSP1_UART4_APPS_CLK		74
93 #define GCC_BLSP1_UART5_APPS_CLK		75
94 #define GCC_BLSP1_UART6_APPS_CLK		76
95 #define GCC_BLSP2_AHB_CLK			77
96 #define GCC_BLSP2_QUP1_I2C_APPS_CLK		78
97 #define GCC_BLSP2_QUP1_SPI_APPS_CLK		79
98 #define GCC_BLSP2_QUP2_I2C_APPS_CLK		80
99 #define GCC_BLSP2_QUP2_SPI_APPS_CLK		81
100 #define GCC_BLSP2_QUP3_I2C_APPS_CLK		82
101 #define GCC_BLSP2_QUP3_SPI_APPS_CLK		83
102 #define GCC_BLSP2_QUP4_I2C_APPS_CLK		84
103 #define GCC_BLSP2_QUP4_SPI_APPS_CLK		85
104 #define GCC_BLSP2_QUP5_I2C_APPS_CLK		86
105 #define GCC_BLSP2_QUP5_SPI_APPS_CLK		87
106 #define GCC_BLSP2_QUP6_I2C_APPS_CLK		88
107 #define GCC_BLSP2_QUP6_SPI_APPS_CLK		89
108 #define GCC_BLSP2_UART1_APPS_CLK		90
109 #define GCC_BLSP2_UART2_APPS_CLK		91
110 #define GCC_BLSP2_UART3_APPS_CLK		92
111 #define GCC_BLSP2_UART4_APPS_CLK		93
112 #define GCC_BLSP2_UART5_APPS_CLK		94
113 #define GCC_BLSP2_UART6_APPS_CLK		95
114 #define GCC_GP1_CLK				96
115 #define GCC_GP2_CLK				97
116 #define GCC_GP3_CLK				98
117 #define GCC_PCIE_0_AUX_CLK			99
118 #define GCC_PCIE_0_PIPE_CLK			100
119 #define GCC_PCIE_1_AUX_CLK			101
120 #define GCC_PCIE_1_PIPE_CLK			102
121 #define GCC_PDM2_CLK				103
122 #define GCC_SDCC1_APPS_CLK			104
123 #define GCC_SDCC2_APPS_CLK			105
124 #define GCC_SDCC3_APPS_CLK			106
125 #define GCC_SDCC4_APPS_CLK			107
126 #define GCC_SYS_NOC_UFS_AXI_CLK			108
127 #define GCC_SYS_NOC_USB3_AXI_CLK		109
128 #define GCC_TSIF_REF_CLK			110
129 #define GCC_UFS_AXI_CLK				111
130 #define GCC_UFS_RX_CFG_CLK			112
131 #define GCC_UFS_TX_CFG_CLK			113
132 #define GCC_USB30_MASTER_CLK			114
133 #define GCC_USB30_MOCK_UTMI_CLK			115
134 #define GCC_USB3_PHY_AUX_CLK			116
135 #define GCC_USB_HS_SYSTEM_CLK			117
136 #define GCC_SDCC1_AHB_CLK			118
137 
138 #endif
139