xref: /linux/include/dt-bindings/clock/qcom,x1e80100-gcc.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1*4dc7e7d2SRajendra Nayak /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*4dc7e7d2SRajendra Nayak /*
3*4dc7e7d2SRajendra Nayak  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4*4dc7e7d2SRajendra Nayak  */
5*4dc7e7d2SRajendra Nayak 
6*4dc7e7d2SRajendra Nayak #ifndef _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
7*4dc7e7d2SRajendra Nayak #define _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
8*4dc7e7d2SRajendra Nayak 
9*4dc7e7d2SRajendra Nayak /* GCC clocks */
10*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK				0
11*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK				1
12*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_UFS_PHY_AXI_CLK				2
13*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB2_PRIM_AXI_CLK				3
14*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB3_MP_AXI_CLK				4
15*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB3_PRIM_AXI_CLK				5
16*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB3_SEC_AXI_CLK				6
17*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB3_TERT_AXI_CLK				7
18*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB4_0_AXI_CLK				8
19*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB4_1_AXI_CLK				9
20*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB4_2_AXI_CLK				10
21*4dc7e7d2SRajendra Nayak #define GCC_AGGRE_USB_NOC_AXI_CLK				11
22*4dc7e7d2SRajendra Nayak #define GCC_AV1E_AHB_CLK					12
23*4dc7e7d2SRajendra Nayak #define GCC_AV1E_AXI_CLK					13
24*4dc7e7d2SRajendra Nayak #define GCC_AV1E_XO_CLK						14
25*4dc7e7d2SRajendra Nayak #define GCC_BOOT_ROM_AHB_CLK					15
26*4dc7e7d2SRajendra Nayak #define GCC_CAMERA_AHB_CLK					16
27*4dc7e7d2SRajendra Nayak #define GCC_CAMERA_HF_AXI_CLK					17
28*4dc7e7d2SRajendra Nayak #define GCC_CAMERA_SF_AXI_CLK					18
29*4dc7e7d2SRajendra Nayak #define GCC_CAMERA_XO_CLK					19
30*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				20
31*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK			21
32*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK			22
33*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB2_PRIM_AXI_CLK				23
34*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB3_MP_AXI_CLK				24
35*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				25
36*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB3_SEC_AXI_CLK				26
37*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB3_TERT_AXI_CLK				27
38*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB_ANOC_AHB_CLK				28
39*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK			29
40*4dc7e7d2SRajendra Nayak #define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK			30
41*4dc7e7d2SRajendra Nayak #define GCC_CNOC_PCIE1_TUNNEL_CLK				31
42*4dc7e7d2SRajendra Nayak #define GCC_CNOC_PCIE2_TUNNEL_CLK				32
43*4dc7e7d2SRajendra Nayak #define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK				33
44*4dc7e7d2SRajendra Nayak #define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK				34
45*4dc7e7d2SRajendra Nayak #define GCC_CNOC_PCIE_TUNNEL_CLK				35
46*4dc7e7d2SRajendra Nayak #define GCC_DDRSS_GPU_AXI_CLK					36
47*4dc7e7d2SRajendra Nayak #define GCC_DISP_AHB_CLK					37
48*4dc7e7d2SRajendra Nayak #define GCC_DISP_HF_AXI_CLK					38
49*4dc7e7d2SRajendra Nayak #define GCC_DISP_XO_CLK						39
50*4dc7e7d2SRajendra Nayak #define GCC_GP1_CLK						40
51*4dc7e7d2SRajendra Nayak #define GCC_GP1_CLK_SRC						41
52*4dc7e7d2SRajendra Nayak #define GCC_GP2_CLK						42
53*4dc7e7d2SRajendra Nayak #define GCC_GP2_CLK_SRC						43
54*4dc7e7d2SRajendra Nayak #define GCC_GP3_CLK						44
55*4dc7e7d2SRajendra Nayak #define GCC_GP3_CLK_SRC						45
56*4dc7e7d2SRajendra Nayak #define GCC_GPLL0						46
57*4dc7e7d2SRajendra Nayak #define GCC_GPLL0_OUT_EVEN					47
58*4dc7e7d2SRajendra Nayak #define GCC_GPLL4						48
59*4dc7e7d2SRajendra Nayak #define GCC_GPLL7						49
60*4dc7e7d2SRajendra Nayak #define GCC_GPLL8						50
61*4dc7e7d2SRajendra Nayak #define GCC_GPLL9						51
62*4dc7e7d2SRajendra Nayak #define GCC_GPU_CFG_AHB_CLK					52
63*4dc7e7d2SRajendra Nayak #define GCC_GPU_GPLL0_CPH_CLK_SRC				53
64*4dc7e7d2SRajendra Nayak #define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC				54
65*4dc7e7d2SRajendra Nayak #define GCC_GPU_MEMNOC_GFX_CLK					55
66*4dc7e7d2SRajendra Nayak #define GCC_GPU_SNOC_DVM_GFX_CLK				56
67*4dc7e7d2SRajendra Nayak #define GCC_PCIE0_PHY_RCHNG_CLK					57
68*4dc7e7d2SRajendra Nayak #define GCC_PCIE1_PHY_RCHNG_CLK					58
69*4dc7e7d2SRajendra Nayak #define GCC_PCIE2_PHY_RCHNG_CLK					59
70*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_AUX_CLK					60
71*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_AUX_CLK_SRC					61
72*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_CFG_AHB_CLK					62
73*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_MSTR_AXI_CLK					63
74*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				64
75*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_PIPE_CLK					65
76*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_SLV_AXI_CLK					66
77*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_SLV_Q2A_AXI_CLK				67
78*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_AUX_CLK					68
79*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_AUX_CLK_SRC					69
80*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_CFG_AHB_CLK					70
81*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_MSTR_AXI_CLK					71
82*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				72
83*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_PIPE_CLK					73
84*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_SLV_AXI_CLK					74
85*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_SLV_Q2A_AXI_CLK				75
86*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_AUX_CLK					76
87*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_AUX_CLK_SRC					77
88*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_CFG_AHB_CLK					78
89*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_MSTR_AXI_CLK					79
90*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_PHY_RCHNG_CLK_SRC				80
91*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_PIPE_CLK					81
92*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_SLV_AXI_CLK					82
93*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_SLV_Q2A_AXI_CLK				83
94*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_AUX_CLK					84
95*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_AUX_CLK_SRC					85
96*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_CFG_AHB_CLK					86
97*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_MSTR_AXI_CLK					87
98*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PHY_AUX_CLK					88
99*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PHY_RCHNG_CLK				89
100*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PHY_RCHNG_CLK_SRC				90
101*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PIPE_CLK					91
102*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PIPE_DIV_CLK_SRC				92
103*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PIPEDIV2_CLK					93
104*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_SLV_AXI_CLK					94
105*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_SLV_Q2A_AXI_CLK				95
106*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_AUX_CLK					96
107*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_AUX_CLK_SRC					97
108*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_CFG_AHB_CLK					98
109*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_MSTR_AXI_CLK					99
110*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PHY_RCHNG_CLK				100
111*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PHY_RCHNG_CLK_SRC				101
112*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PIPE_CLK					102
113*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PIPE_DIV_CLK_SRC				103
114*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PIPEDIV2_CLK					104
115*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_SLV_AXI_CLK					105
116*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_SLV_Q2A_AXI_CLK				106
117*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_AUX_CLK					107
118*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_AUX_CLK_SRC					108
119*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_CFG_AHB_CLK					109
120*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_MSTR_AXI_CLK					110
121*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PHY_RCHNG_CLK				111
122*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PHY_RCHNG_CLK_SRC				112
123*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PIPE_CLK					113
124*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PIPE_DIV_CLK_SRC				114
125*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PIPEDIV2_CLK					115
126*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_SLV_AXI_CLK					116
127*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_SLV_Q2A_AXI_CLK				117
128*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_AUX_CLK					118
129*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_AUX_CLK_SRC					119
130*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_CFG_AHB_CLK					120
131*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_MSTR_AXI_CLK				121
132*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PHY_AUX_CLK					122
133*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PHY_RCHNG_CLK				123
134*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC				124
135*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PIPE_CLK					125
136*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PIPE_DIV_CLK_SRC				126
137*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PIPEDIV2_CLK				127
138*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_SLV_AXI_CLK					128
139*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_SLV_Q2A_AXI_CLK				129
140*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_AUX_CLK					130
141*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_AUX_CLK_SRC					131
142*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_CFG_AHB_CLK					132
143*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_MSTR_AXI_CLK				133
144*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PHY_AUX_CLK					134
145*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PHY_RCHNG_CLK				135
146*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC				136
147*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PIPE_CLK					137
148*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PIPE_DIV_CLK_SRC				138
149*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PIPEDIV2_CLK				139
150*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_SLV_AXI_CLK					140
151*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_SLV_Q2A_AXI_CLK				141
152*4dc7e7d2SRajendra Nayak #define GCC_PCIE_RSCC_AHB_CLK					142
153*4dc7e7d2SRajendra Nayak #define GCC_PCIE_RSCC_XO_CLK					143
154*4dc7e7d2SRajendra Nayak #define GCC_PCIE_RSCC_XO_CLK_SRC				144
155*4dc7e7d2SRajendra Nayak #define GCC_PDM2_CLK						145
156*4dc7e7d2SRajendra Nayak #define GCC_PDM2_CLK_SRC					146
157*4dc7e7d2SRajendra Nayak #define GCC_PDM_AHB_CLK						147
158*4dc7e7d2SRajendra Nayak #define GCC_PDM_XO4_CLK						148
159*4dc7e7d2SRajendra Nayak #define GCC_QMIP_AV1E_AHB_CLK					149
160*4dc7e7d2SRajendra Nayak #define GCC_QMIP_CAMERA_NRT_AHB_CLK				150
161*4dc7e7d2SRajendra Nayak #define GCC_QMIP_CAMERA_RT_AHB_CLK				151
162*4dc7e7d2SRajendra Nayak #define GCC_QMIP_DISP_AHB_CLK					152
163*4dc7e7d2SRajendra Nayak #define GCC_QMIP_GPU_AHB_CLK					153
164*4dc7e7d2SRajendra Nayak #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				154
165*4dc7e7d2SRajendra Nayak #define GCC_QMIP_VIDEO_CVP_AHB_CLK				155
166*4dc7e7d2SRajendra Nayak #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				156
167*4dc7e7d2SRajendra Nayak #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				157
168*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_CORE_2X_CLK				158
169*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_CORE_CLK				159
170*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_QSPI_S2_CLK				160
171*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_QSPI_S3_CLK				161
172*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S0_CLK					162
173*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S0_CLK_SRC				163
174*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S1_CLK					164
175*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S1_CLK_SRC				165
176*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S2_CLK					166
177*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S2_CLK_SRC				167
178*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC				168
179*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S3_CLK					169
180*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S3_CLK_SRC				170
181*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC				171
182*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S4_CLK					172
183*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S4_CLK_SRC				173
184*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S5_CLK					174
185*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S5_CLK_SRC				175
186*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S6_CLK					176
187*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S6_CLK_SRC				177
188*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S7_CLK					178
189*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP0_S7_CLK_SRC				179
190*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_CORE_2X_CLK				180
191*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_CORE_CLK				181
192*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_QSPI_S2_CLK				182
193*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_QSPI_S3_CLK				183
194*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S0_CLK					184
195*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S0_CLK_SRC				185
196*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S1_CLK					186
197*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S1_CLK_SRC				187
198*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S2_CLK					188
199*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S2_CLK_SRC				189
200*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC				190
201*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S3_CLK					191
202*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S3_CLK_SRC				192
203*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC				193
204*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S4_CLK					194
205*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S4_CLK_SRC				195
206*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S5_CLK					196
207*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S5_CLK_SRC				197
208*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S6_CLK					198
209*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S6_CLK_SRC				199
210*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S7_CLK					200
211*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP1_S7_CLK_SRC				201
212*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_CORE_2X_CLK				202
213*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_CORE_CLK				203
214*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_QSPI_S2_CLK				204
215*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_QSPI_S3_CLK				205
216*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S0_CLK					206
217*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S0_CLK_SRC				207
218*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S1_CLK					208
219*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S1_CLK_SRC				209
220*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S2_CLK					210
221*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S2_CLK_SRC				211
222*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC				212
223*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S3_CLK					213
224*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S3_CLK_SRC				214
225*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC				215
226*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S4_CLK					216
227*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S4_CLK_SRC				217
228*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S5_CLK					218
229*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S5_CLK_SRC				219
230*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S6_CLK					220
231*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S6_CLK_SRC				221
232*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S7_CLK					222
233*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP2_S7_CLK_SRC				223
234*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP_0_M_AHB_CLK				224
235*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP_0_S_AHB_CLK				225
236*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP_1_M_AHB_CLK				226
237*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP_1_S_AHB_CLK				227
238*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP_2_M_AHB_CLK				228
239*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAP_2_S_AHB_CLK				229
240*4dc7e7d2SRajendra Nayak #define GCC_SDCC2_AHB_CLK					230
241*4dc7e7d2SRajendra Nayak #define GCC_SDCC2_APPS_CLK					231
242*4dc7e7d2SRajendra Nayak #define GCC_SDCC2_APPS_CLK_SRC					232
243*4dc7e7d2SRajendra Nayak #define GCC_SDCC4_AHB_CLK					233
244*4dc7e7d2SRajendra Nayak #define GCC_SDCC4_APPS_CLK					234
245*4dc7e7d2SRajendra Nayak #define GCC_SDCC4_APPS_CLK_SRC					235
246*4dc7e7d2SRajendra Nayak #define GCC_SYS_NOC_USB_AXI_CLK					236
247*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_AHB_CLK					237
248*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_AXI_CLK					238
249*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_AXI_CLK_SRC					239
250*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_ICE_CORE_CLK				240
251*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_ICE_CORE_CLK_SRC				241
252*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_PHY_AUX_CLK					242
253*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_PHY_AUX_CLK_SRC				243
254*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_RX_SYMBOL_0_CLK				244
255*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_RX_SYMBOL_1_CLK				245
256*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_TX_SYMBOL_0_CLK				246
257*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_UNIPRO_CORE_CLK				247
258*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				248
259*4dc7e7d2SRajendra Nayak #define GCC_USB20_MASTER_CLK					249
260*4dc7e7d2SRajendra Nayak #define GCC_USB20_MASTER_CLK_SRC				250
261*4dc7e7d2SRajendra Nayak #define GCC_USB20_MOCK_UTMI_CLK					251
262*4dc7e7d2SRajendra Nayak #define GCC_USB20_MOCK_UTMI_CLK_SRC				252
263*4dc7e7d2SRajendra Nayak #define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC			253
264*4dc7e7d2SRajendra Nayak #define GCC_USB20_SLEEP_CLK					254
265*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_MASTER_CLK					255
266*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_MASTER_CLK_SRC				256
267*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_MOCK_UTMI_CLK				257
268*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_MOCK_UTMI_CLK_SRC				258
269*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC			259
270*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_SLEEP_CLK					260
271*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_MASTER_CLK				261
272*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_MASTER_CLK_SRC				262
273*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_MOCK_UTMI_CLK				263
274*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			264
275*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		265
276*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_SLEEP_CLK				266
277*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_MASTER_CLK				267
278*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_MASTER_CLK_SRC				268
279*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_MOCK_UTMI_CLK				269
280*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				270
281*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			271
282*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_SLEEP_CLK					272
283*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_MASTER_CLK				273
284*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_MASTER_CLK_SRC				274
285*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_MOCK_UTMI_CLK				275
286*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC			276
287*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC		277
288*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_SLEEP_CLK				278
289*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_PHY_AUX_CLK					279
290*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_PHY_AUX_CLK_SRC				280
291*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_PHY_COM_AUX_CLK				281
292*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_PHY_PIPE_0_CLK				282
293*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_PHY_PIPE_1_CLK				283
294*4dc7e7d2SRajendra Nayak #define GCC_USB3_PRIM_PHY_AUX_CLK				284
295*4dc7e7d2SRajendra Nayak #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				285
296*4dc7e7d2SRajendra Nayak #define GCC_USB3_PRIM_PHY_COM_AUX_CLK				286
297*4dc7e7d2SRajendra Nayak #define GCC_USB3_PRIM_PHY_PIPE_CLK				287
298*4dc7e7d2SRajendra Nayak #define GCC_USB3_SEC_PHY_AUX_CLK				288
299*4dc7e7d2SRajendra Nayak #define GCC_USB3_SEC_PHY_AUX_CLK_SRC				289
300*4dc7e7d2SRajendra Nayak #define GCC_USB3_SEC_PHY_COM_AUX_CLK				290
301*4dc7e7d2SRajendra Nayak #define GCC_USB3_SEC_PHY_PIPE_CLK				291
302*4dc7e7d2SRajendra Nayak #define GCC_USB3_TERT_PHY_AUX_CLK				292
303*4dc7e7d2SRajendra Nayak #define GCC_USB3_TERT_PHY_AUX_CLK_SRC				293
304*4dc7e7d2SRajendra Nayak #define GCC_USB3_TERT_PHY_COM_AUX_CLK				294
305*4dc7e7d2SRajendra Nayak #define GCC_USB3_TERT_PHY_PIPE_CLK				295
306*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_CFG_AHB_CLK					296
307*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_DP0_CLK					297
308*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_DP1_CLK					298
309*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_MASTER_CLK					299
310*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_MASTER_CLK_SRC				300
311*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK				301
312*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_PHY_PCIE_PIPE_CLK				302
313*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC			303
314*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_PHY_RX0_CLK					304
315*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_PHY_RX1_CLK					305
316*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_PHY_USB_PIPE_CLK				306
317*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_SB_IF_CLK					307
318*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_SB_IF_CLK_SRC				308
319*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_SYS_CLK					309
320*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_TMU_CLK					310
321*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_TMU_CLK_SRC					311
322*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_CFG_AHB_CLK					312
323*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_DP0_CLK					313
324*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_DP1_CLK					314
325*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_MASTER_CLK					315
326*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_MASTER_CLK_SRC				316
327*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK				317
328*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_PHY_PCIE_PIPE_CLK				318
329*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC			319
330*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_PHY_RX0_CLK					320
331*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_PHY_RX1_CLK					321
332*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_PHY_USB_PIPE_CLK				322
333*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_SB_IF_CLK					323
334*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_SB_IF_CLK_SRC				324
335*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_SYS_CLK					325
336*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_TMU_CLK					326
337*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_TMU_CLK_SRC					327
338*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_CFG_AHB_CLK					328
339*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_DP0_CLK					329
340*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_DP1_CLK					330
341*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_MASTER_CLK					331
342*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_MASTER_CLK_SRC				332
343*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK				333
344*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_PHY_PCIE_PIPE_CLK				334
345*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC			335
346*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_PHY_RX0_CLK					336
347*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_PHY_RX1_CLK					337
348*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_PHY_USB_PIPE_CLK				338
349*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_SB_IF_CLK					339
350*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_SB_IF_CLK_SRC				340
351*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_SYS_CLK					341
352*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_TMU_CLK					342
353*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_TMU_CLK_SRC					343
354*4dc7e7d2SRajendra Nayak #define GCC_VIDEO_AHB_CLK					344
355*4dc7e7d2SRajendra Nayak #define GCC_VIDEO_AXI0_CLK					345
356*4dc7e7d2SRajendra Nayak #define GCC_VIDEO_AXI1_CLK					346
357*4dc7e7d2SRajendra Nayak #define GCC_VIDEO_XO_CLK					347
358*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PIPE_CLK_SRC					348
359*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PIPE_CLK_SRC					349
360*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PIPE_CLK_SRC					350
361*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PIPE_CLK_SRC				351
362*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PIPE_CLK_SRC				352
363*4dc7e7d2SRajendra Nayak #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				353
364*4dc7e7d2SRajendra Nayak #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				354
365*4dc7e7d2SRajendra Nayak #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC				355
366*4dc7e7d2SRajendra Nayak 
367*4dc7e7d2SRajendra Nayak /* GCC power domains */
368*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_TUNNEL_GDSC					0
369*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_TUNNEL_GDSC					1
370*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_TUNNEL_GDSC					2
371*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_GDSC						3
372*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PHY_GDSC					4
373*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_GDSC						5
374*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PHY_GDSC					6
375*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_GDSC						7
376*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PHY_GDSC					8
377*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6_PHY_GDSC					9
378*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_GDSC					10
379*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_GDSC					11
380*4dc7e7d2SRajendra Nayak #define GCC_UFS_MEM_PHY_GDSC					12
381*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_GDSC					13
382*4dc7e7d2SRajendra Nayak #define GCC_USB20_PRIM_GDSC					14
383*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_GDSC					15
384*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_GDSC					16
385*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_GDSC					17
386*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_GDSC					18
387*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_SS0_PHY_GDSC				19
388*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_SS1_PHY_GDSC				20
389*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_GDSC						21
390*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_GDSC						22
391*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_GDSC						23
392*4dc7e7d2SRajendra Nayak #define GCC_USB_0_PHY_GDSC					24
393*4dc7e7d2SRajendra Nayak #define GCC_USB_1_PHY_GDSC					25
394*4dc7e7d2SRajendra Nayak #define GCC_USB_2_PHY_GDSC					26
395*4dc7e7d2SRajendra Nayak 
396*4dc7e7d2SRajendra Nayak /* GCC resets */
397*4dc7e7d2SRajendra Nayak #define GCC_AV1E_BCR						0
398*4dc7e7d2SRajendra Nayak #define GCC_CAMERA_BCR						1
399*4dc7e7d2SRajendra Nayak #define GCC_DISPLAY_BCR						2
400*4dc7e7d2SRajendra Nayak #define GCC_GPU_BCR						3
401*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_LINK_DOWN_BCR				4
402*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_NOCSR_COM_PHY_BCR				5
403*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_PHY_BCR					6
404*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			7
405*4dc7e7d2SRajendra Nayak #define GCC_PCIE_0_TUNNEL_BCR					8
406*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_LINK_DOWN_BCR				9
407*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_NOCSR_COM_PHY_BCR				10
408*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_PHY_BCR					11
409*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			12
410*4dc7e7d2SRajendra Nayak #define GCC_PCIE_1_TUNNEL_BCR					13
411*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_LINK_DOWN_BCR				14
412*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_NOCSR_COM_PHY_BCR				15
413*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_PHY_BCR					16
414*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR			17
415*4dc7e7d2SRajendra Nayak #define GCC_PCIE_2_TUNNEL_BCR					18
416*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_BCR						19
417*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_LINK_DOWN_BCR				20
418*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_NOCSR_COM_PHY_BCR				21
419*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PHY_BCR					22
420*4dc7e7d2SRajendra Nayak #define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR			23
421*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_BCR						24
422*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_LINK_DOWN_BCR				25
423*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_NOCSR_COM_PHY_BCR				26
424*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PHY_BCR					27
425*4dc7e7d2SRajendra Nayak #define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR			28
426*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_BCR						29
427*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_LINK_DOWN_BCR				30
428*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_NOCSR_COM_PHY_BCR				31
429*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PHY_BCR					32
430*4dc7e7d2SRajendra Nayak #define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR			33
431*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_BCR						34
432*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_LINK_DOWN_BCR				35
433*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_NOCSR_COM_PHY_BCR				36
434*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PHY_BCR					37
435*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR			38
436*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_BCR						39
437*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_LINK_DOWN_BCR				40
438*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_NOCSR_COM_PHY_BCR				41
439*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PHY_BCR					42
440*4dc7e7d2SRajendra Nayak #define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR			43
441*4dc7e7d2SRajendra Nayak #define GCC_PCIE_PHY_BCR					44
442*4dc7e7d2SRajendra Nayak #define GCC_PCIE_PHY_CFG_AHB_BCR				45
443*4dc7e7d2SRajendra Nayak #define GCC_PCIE_PHY_COM_BCR					46
444*4dc7e7d2SRajendra Nayak #define GCC_PCIE_RSCC_BCR					47
445*4dc7e7d2SRajendra Nayak #define GCC_PDM_BCR						48
446*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAPPER_0_BCR					49
447*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAPPER_1_BCR					50
448*4dc7e7d2SRajendra Nayak #define GCC_QUPV3_WRAPPER_2_BCR					51
449*4dc7e7d2SRajendra Nayak #define GCC_QUSB2PHY_HS0_MP_BCR					52
450*4dc7e7d2SRajendra Nayak #define GCC_QUSB2PHY_HS1_MP_BCR					53
451*4dc7e7d2SRajendra Nayak #define GCC_QUSB2PHY_PRIM_BCR					54
452*4dc7e7d2SRajendra Nayak #define GCC_QUSB2PHY_SEC_BCR					55
453*4dc7e7d2SRajendra Nayak #define GCC_QUSB2PHY_TERT_BCR					56
454*4dc7e7d2SRajendra Nayak #define GCC_QUSB2PHY_USB20_HS_BCR				57
455*4dc7e7d2SRajendra Nayak #define GCC_SDCC2_BCR						58
456*4dc7e7d2SRajendra Nayak #define GCC_SDCC4_BCR						59
457*4dc7e7d2SRajendra Nayak #define GCC_UFS_PHY_BCR						60
458*4dc7e7d2SRajendra Nayak #define GCC_USB20_PRIM_BCR					61
459*4dc7e7d2SRajendra Nayak #define GCC_USB30_MP_BCR					62
460*4dc7e7d2SRajendra Nayak #define GCC_USB30_PRIM_BCR					63
461*4dc7e7d2SRajendra Nayak #define GCC_USB30_SEC_BCR					64
462*4dc7e7d2SRajendra Nayak #define GCC_USB30_TERT_BCR					65
463*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_SS0_PHY_BCR					66
464*4dc7e7d2SRajendra Nayak #define GCC_USB3_MP_SS1_PHY_BCR					67
465*4dc7e7d2SRajendra Nayak #define GCC_USB3_PHY_PRIM_BCR					68
466*4dc7e7d2SRajendra Nayak #define GCC_USB3_PHY_SEC_BCR					69
467*4dc7e7d2SRajendra Nayak #define GCC_USB3_PHY_TERT_BCR					70
468*4dc7e7d2SRajendra Nayak #define GCC_USB3_UNIPHY_MP0_BCR					71
469*4dc7e7d2SRajendra Nayak #define GCC_USB3_UNIPHY_MP1_BCR					72
470*4dc7e7d2SRajendra Nayak #define GCC_USB3PHY_PHY_PRIM_BCR				73
471*4dc7e7d2SRajendra Nayak #define GCC_USB3PHY_PHY_SEC_BCR					74
472*4dc7e7d2SRajendra Nayak #define GCC_USB3PHY_PHY_TERT_BCR				75
473*4dc7e7d2SRajendra Nayak #define GCC_USB3UNIPHY_PHY_MP0_BCR				76
474*4dc7e7d2SRajendra Nayak #define GCC_USB3UNIPHY_PHY_MP1_BCR				77
475*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_BCR						78
476*4dc7e7d2SRajendra Nayak #define GCC_USB4_0_DP0_PHY_PRIM_BCR				79
477*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_DP0_PHY_SEC_BCR				80
478*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_DP0_PHY_TERT_BCR				81
479*4dc7e7d2SRajendra Nayak #define GCC_USB4_1_BCR						82
480*4dc7e7d2SRajendra Nayak #define GCC_USB4_2_BCR						83
481*4dc7e7d2SRajendra Nayak #define GCC_USB_0_PHY_BCR					84
482*4dc7e7d2SRajendra Nayak #define GCC_USB_1_PHY_BCR					85
483*4dc7e7d2SRajendra Nayak #define GCC_USB_2_PHY_BCR					86
484*4dc7e7d2SRajendra Nayak #define GCC_VIDEO_BCR						87
485*4dc7e7d2SRajendra Nayak #endif
486