1f92b7782SKathiravan Thirumoorthy /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2f92b7782SKathiravan Thirumoorthy /* 3f92b7782SKathiravan Thirumoorthy * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4f92b7782SKathiravan Thirumoorthy */ 5f92b7782SKathiravan Thirumoorthy 6f92b7782SKathiravan Thirumoorthy #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H 7f92b7782SKathiravan Thirumoorthy #define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H 8f92b7782SKathiravan Thirumoorthy 9f92b7782SKathiravan Thirumoorthy #define GCC_ADSS_PWM_CLK 0 10f92b7782SKathiravan Thirumoorthy #define GCC_ADSS_PWM_CLK_SRC 1 11f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE0_1LANE_M_CLK 2 12f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE0_1LANE_S_CLK 3 13f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE1_2LANE_M_CLK 4 14f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE1_2LANE_S_CLK 5 15f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE2_2LANE_M_CLK 6 16f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE2_2LANE_S_CLK 7 17f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE3_2LANE_M_CLK 8 18f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE3_2LANE_S_CLK 9 19f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE4_1LANE_M_CLK 10 20f92b7782SKathiravan Thirumoorthy #define GCC_ANOC_PCIE4_1LANE_S_CLK 11 21f92b7782SKathiravan Thirumoorthy #define GCC_CMN_12GPLL_AHB_CLK 12 22f92b7782SKathiravan Thirumoorthy #define GCC_CMN_12GPLL_APU_CLK 13 23f92b7782SKathiravan Thirumoorthy #define GCC_CMN_12GPLL_SYS_CLK 14 24f92b7782SKathiravan Thirumoorthy #define GCC_CMN_LDO_CLK 15 25f92b7782SKathiravan Thirumoorthy #define GCC_MDIO_AHB_CLK 16 26f92b7782SKathiravan Thirumoorthy #define GCC_NSSCC_CLK 17 27f92b7782SKathiravan Thirumoorthy #define GCC_NSSCFG_CLK 18 28f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_ATB_CLK 19 29f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_1_CLK 20 30f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 31f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_CLK 22 32f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 33f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_NSSCC_CLK 24 34f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_PCNOC_1_CLK 25 35f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_QOSGEN_REF_CLK 26 36f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_SNOC_1_CLK 27 37f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_SNOC_CLK 28 38f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_TIMEOUT_REF_CLK 29 39f92b7782SKathiravan Thirumoorthy #define GCC_NSSNOC_XO_DCD_CLK 30 40f92b7782SKathiravan Thirumoorthy #define GCC_NSS_TS_CLK 31 41f92b7782SKathiravan Thirumoorthy #define GCC_NSS_TS_CLK_SRC 32 42f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AHB_CLK 33 43f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AUX_CLK 34 44f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_M_CLK 35 45f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_M_CLK_SRC 36 46f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_BRIDGE_CLK 37 47f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_CLK 38 48f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_CLK_SRC 39 49f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_PIPE_CLK 40 50f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_PIPE_CLK_SRC 41 51f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_RCHNG_CLK 42 52f92b7782SKathiravan Thirumoorthy #define GCC_PCIE0_RCHNG_CLK_SRC 43 53f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AHB_CLK 44 54f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AUX_CLK 45 55f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_M_CLK 46 56f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_M_CLK_SRC 47 57f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_BRIDGE_CLK 48 58f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_CLK 49 59f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_CLK_SRC 50 60f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_PIPE_CLK 51 61f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_PIPE_CLK_SRC 52 62f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_RCHNG_CLK 53 63f92b7782SKathiravan Thirumoorthy #define GCC_PCIE1_RCHNG_CLK_SRC 54 64f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AHB_CLK 55 65f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AUX_CLK 56 66f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_M_CLK 57 67f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_M_CLK_SRC 58 68f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_S_BRIDGE_CLK 59 69f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_S_CLK 60 70f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_AXI_S_CLK_SRC 61 71f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_PIPE_CLK 62 72f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_PIPE_CLK_SRC 63 73f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_RCHNG_CLK 64 74f92b7782SKathiravan Thirumoorthy #define GCC_PCIE2_RCHNG_CLK_SRC 65 75f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AHB_CLK 66 76f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AUX_CLK 67 77f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_M_CLK 68 78f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_M_CLK_SRC 69 79f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_S_BRIDGE_CLK 70 80f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_S_CLK 71 81f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_AXI_S_CLK_SRC 72 82f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_PIPE_CLK 73 83f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_PIPE_CLK_SRC 74 84f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_RCHNG_CLK 75 85f92b7782SKathiravan Thirumoorthy #define GCC_PCIE3_RCHNG_CLK_SRC 76 86f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AHB_CLK 77 87f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AUX_CLK 78 88f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_M_CLK 79 89f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_M_CLK_SRC 80 90f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_S_BRIDGE_CLK 81 91f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_S_CLK 82 92f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_AXI_S_CLK_SRC 83 93f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_PIPE_CLK 84 94f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_PIPE_CLK_SRC 85 95f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_RCHNG_CLK 86 96f92b7782SKathiravan Thirumoorthy #define GCC_PCIE4_RCHNG_CLK_SRC 87 97f92b7782SKathiravan Thirumoorthy #define GCC_PCIE_AUX_CLK_SRC 88 98f92b7782SKathiravan Thirumoorthy #define GCC_PCNOC_BFDCD_CLK_SRC 89 99f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_AT_CLK 90 100f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_AT_CLK_SRC 91 101f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_DAP_CLK 92 102f92b7782SKathiravan Thirumoorthy #define GCC_QDSS_TSCTR_CLK_SRC 93 103f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_AHB_CLK 94 104f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_CLK 95 105f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_CLK_SRC 96 106f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_IO_MACRO_CLK 97 107f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_IO_MACRO_CLK_SRC 98 108f92b7782SKathiravan Thirumoorthy #define GCC_QPIC_SLEEP_CLK 99 109f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_2X_CORE_CLK 100 110f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_2X_CORE_CLK_SRC 101 111f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_AHB_MST_CLK 102 112f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_AHB_SLV_CLK 103 113f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_CORE_CLK 104 114f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_SLEEP_CLK 105 115f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE0_CLK 106 116f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE0_CLK_SRC 107 117f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE1_CLK 108 118f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE1_CLK_SRC 109 119f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE2_CLK 110 120f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE2_CLK_SRC 111 121f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE3_CLK 112 122f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE3_CLK_SRC 113 123f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE4_CLK 114 124f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE4_CLK_SRC 115 125f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE5_CLK 116 126f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE5_CLK_SRC 117 127f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE6_CLK 118 128f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE6_CLK_SRC 119 129f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE7_CLK 120 130f92b7782SKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE7_CLK_SRC 121 131f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_AHB_CLK 122 132f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_APPS_CLK 123 133f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_APPS_CLK_SRC 124 134f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_ICE_CORE_CLK 125 135f92b7782SKathiravan Thirumoorthy #define GCC_SDCC1_ICE_CORE_CLK_SRC 126 136f92b7782SKathiravan Thirumoorthy #define GCC_SLEEP_CLK_SRC 127 137f92b7782SKathiravan Thirumoorthy #define GCC_SNOC_USB_CLK 128 138f92b7782SKathiravan Thirumoorthy #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 139f92b7782SKathiravan Thirumoorthy #define GCC_TLMM_AHB_CLK 130 140f92b7782SKathiravan Thirumoorthy #define GCC_TLMM_CLK 131 141f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY0_AHB_CLK 132 142f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY0_SYS_CLK 133 143f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY1_AHB_CLK 134 144f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY1_SYS_CLK 135 145f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY2_AHB_CLK 136 146f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY2_SYS_CLK 137 147f92b7782SKathiravan Thirumoorthy #define GCC_UNIPHY_SYS_CLK_SRC 138 148f92b7782SKathiravan Thirumoorthy #define GCC_USB0_AUX_CLK 139 149f92b7782SKathiravan Thirumoorthy #define GCC_USB0_AUX_CLK_SRC 140 150f92b7782SKathiravan Thirumoorthy #define GCC_USB0_EUD_AT_CLK 141 151f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MASTER_CLK 142 152f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MASTER_CLK_SRC 143 153f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_CLK 144 154f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_CLK_SRC 145 155f92b7782SKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 146 156f92b7782SKathiravan Thirumoorthy #define GCC_USB0_PHY_CFG_AHB_CLK 147 157f92b7782SKathiravan Thirumoorthy #define GCC_USB0_PIPE_CLK 148 158f92b7782SKathiravan Thirumoorthy #define GCC_USB0_PIPE_CLK_SRC 149 159f92b7782SKathiravan Thirumoorthy #define GCC_USB0_SLEEP_CLK 150 160f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MASTER_CLK 151 161f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MOCK_UTMI_CLK 152 162f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MOCK_UTMI_CLK_SRC 153 163f92b7782SKathiravan Thirumoorthy #define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 154 164f92b7782SKathiravan Thirumoorthy #define GCC_USB1_PHY_CFG_AHB_CLK 155 165f92b7782SKathiravan Thirumoorthy #define GCC_USB1_SLEEP_CLK 156 166f92b7782SKathiravan Thirumoorthy #define GCC_XO_CLK_SRC 157 167f92b7782SKathiravan Thirumoorthy #define GPLL0 158 168f92b7782SKathiravan Thirumoorthy #define GPLL0_MAIN 159 169f92b7782SKathiravan Thirumoorthy #define GPLL2 160 170f92b7782SKathiravan Thirumoorthy #define GPLL2_OUT_MAIN 161 171f92b7782SKathiravan Thirumoorthy #define GPLL4 162 172*dd7ddd05SKathiravan Thirumoorthy #define GCC_REFGEN_CORE_CLK_SRC 163 173*dd7ddd05SKathiravan Thirumoorthy #define GCC_REFGEN_PCIE_CORE_CLK 164 174*dd7ddd05SKathiravan Thirumoorthy #define GCC_REFGEN_PCIE_HCLK 165 175*dd7ddd05SKathiravan Thirumoorthy #define GCC_REFGEN_CMN_UPHY_HCLK 166 176*dd7ddd05SKathiravan Thirumoorthy #define GCC_REFGEN_CMN_UPHY_CORE_CLK 167 177f92b7782SKathiravan Thirumoorthy #endif 178