1 /* 2 * Copyright 2017 Texas Instruments, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #ifndef __DT_BINDINGS_CLK_OMAP5_H 14 #define __DT_BINDINGS_CLK_OMAP5_H 15 16 #define OMAP5_CLKCTRL_OFFSET 0x20 17 #define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) 18 19 /* mpu clocks */ 20 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 21 22 /* dsp clocks */ 23 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 24 25 /* abe clocks */ 26 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 27 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 28 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 29 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) 30 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 31 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) 32 #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 33 #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) 34 #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 35 #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) 36 37 /* l3main1 clocks */ 38 #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 39 40 /* l3main2 clocks */ 41 #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 42 43 /* ipu clocks */ 44 #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 45 46 /* dma clocks */ 47 #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 48 49 /* emif clocks */ 50 #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 51 #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 52 #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 53 54 /* l4cfg clocks */ 55 #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 56 #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 57 #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 58 59 /* l3instr clocks */ 60 #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 61 #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 62 63 /* l4per clocks */ 64 #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 65 #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 66 #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 67 #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) 68 #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) 69 #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 70 #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) 71 #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 72 #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) 73 #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 74 #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) 75 #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) 76 #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) 77 #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) 78 #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) 79 #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) 80 #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) 81 #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) 82 #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) 83 #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) 84 #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) 85 #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) 86 #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) 87 #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) 88 #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) 89 #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) 90 #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) 91 #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) 92 #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) 93 #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) 94 #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) 95 #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) 96 97 /* dss clocks */ 98 #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 99 100 /* l3init clocks */ 101 #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 102 #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 103 #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) 104 #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 105 #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) 106 #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) 107 #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) 108 #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) 109 110 /* wkupaon clocks */ 111 #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 112 #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 113 #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 114 #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) 115 #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 116 #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 117 118 #endif 119