1*977b07f7SPeng Fan /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2*977b07f7SPeng Fan /* 3*977b07f7SPeng Fan * Copyright 2024 NXP 4*977b07f7SPeng Fan */ 5*977b07f7SPeng Fan 6*977b07f7SPeng Fan #ifndef __DT_BINDINGS_CLOCK_IMX95_H 7*977b07f7SPeng Fan #define __DT_BINDINGS_CLOCK_IMX95_H 8*977b07f7SPeng Fan 9*977b07f7SPeng Fan #define IMX95_CLK_VPUBLK_WAVE 0 10*977b07f7SPeng Fan #define IMX95_CLK_VPUBLK_JPEG_ENC 1 11*977b07f7SPeng Fan #define IMX95_CLK_VPUBLK_JPEG_DEC 2 12*977b07f7SPeng Fan 13*977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_CSI2_FOR0 0 14*977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_CSI2_FOR1 1 15*977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_ISP_AXI 2 16*977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_ISP_PIXEL 3 17*977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_ISP 4 18*977b07f7SPeng Fan 19*977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 20*977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 21*977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 22*977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 23*977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 24*977b07f7SPeng Fan 25*977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_ENG0_SEL 0 26*977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_ENG1_SEL 1 27*977b07f7SPeng Fan 28*977b07f7SPeng Fan #endif /* __DT_BINDINGS_CLOCK_IMX95_H */ 29