1977b07f7SPeng Fan /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2977b07f7SPeng Fan /* 3977b07f7SPeng Fan * Copyright 2024 NXP 4977b07f7SPeng Fan */ 5977b07f7SPeng Fan 6977b07f7SPeng Fan #ifndef __DT_BINDINGS_CLOCK_IMX95_H 7977b07f7SPeng Fan #define __DT_BINDINGS_CLOCK_IMX95_H 8977b07f7SPeng Fan 9977b07f7SPeng Fan #define IMX95_CLK_VPUBLK_WAVE 0 10977b07f7SPeng Fan #define IMX95_CLK_VPUBLK_JPEG_ENC 1 11977b07f7SPeng Fan #define IMX95_CLK_VPUBLK_JPEG_DEC 2 12977b07f7SPeng Fan 13977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_CSI2_FOR0 0 14977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_CSI2_FOR1 1 15977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_ISP_AXI 2 16977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_ISP_PIXEL 3 17977b07f7SPeng Fan #define IMX95_CLK_CAMBLK_ISP 4 18977b07f7SPeng Fan 19977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 20977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 21977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 22977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 23977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 24977b07f7SPeng Fan 25977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_ENG0_SEL 0 26977b07f7SPeng Fan #define IMX95_CLK_DISPMIX_ENG1_SEL 1 27977b07f7SPeng Fan 28*b4f62001SWei Fang #define IMX95_CLK_NETCMIX_ENETC0_RMII 0 29*b4f62001SWei Fang #define IMX95_CLK_NETCMIX_ENETC1_RMII 1 30*b4f62001SWei Fang 31977b07f7SPeng Fan #endif /* __DT_BINDINGS_CLOCK_IMX95_H */ 32