1*08e95044STomer Maimon /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*08e95044STomer Maimon /* 3*08e95044STomer Maimon * Copyright (C) 2021 Nuvoton Technologies. 4*08e95044STomer Maimon * Author: Tomer Maimon <tomer.maimon@nuvoton.com> 5*08e95044STomer Maimon * 6*08e95044STomer Maimon * Device Tree binding constants for NPCM8XX clock controller. 7*08e95044STomer Maimon */ 8*08e95044STomer Maimon 9*08e95044STomer Maimon #ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H 10*08e95044STomer Maimon #define __DT_BINDINGS_CLOCK_NPCM8XX_H 11*08e95044STomer Maimon 12*08e95044STomer Maimon #define NPCM8XX_CLK_CPU 0 13*08e95044STomer Maimon #define NPCM8XX_CLK_GFX_PIXEL 1 14*08e95044STomer Maimon #define NPCM8XX_CLK_MC 2 15*08e95044STomer Maimon #define NPCM8XX_CLK_ADC 3 16*08e95044STomer Maimon #define NPCM8XX_CLK_AHB 4 17*08e95044STomer Maimon #define NPCM8XX_CLK_TIMER 5 18*08e95044STomer Maimon #define NPCM8XX_CLK_UART 6 19*08e95044STomer Maimon #define NPCM8XX_CLK_UART2 7 20*08e95044STomer Maimon #define NPCM8XX_CLK_MMC 8 21*08e95044STomer Maimon #define NPCM8XX_CLK_SPI3 9 22*08e95044STomer Maimon #define NPCM8XX_CLK_PCI 10 23*08e95044STomer Maimon #define NPCM8XX_CLK_AXI 11 24*08e95044STomer Maimon #define NPCM8XX_CLK_APB4 12 25*08e95044STomer Maimon #define NPCM8XX_CLK_APB3 13 26*08e95044STomer Maimon #define NPCM8XX_CLK_APB2 14 27*08e95044STomer Maimon #define NPCM8XX_CLK_APB1 15 28*08e95044STomer Maimon #define NPCM8XX_CLK_APB5 16 29*08e95044STomer Maimon #define NPCM8XX_CLK_CLKOUT 17 30*08e95044STomer Maimon #define NPCM8XX_CLK_GFX 18 31*08e95044STomer Maimon #define NPCM8XX_CLK_SU 19 32*08e95044STomer Maimon #define NPCM8XX_CLK_SU48 20 33*08e95044STomer Maimon #define NPCM8XX_CLK_SDHC 21 34*08e95044STomer Maimon #define NPCM8XX_CLK_SPI0 22 35*08e95044STomer Maimon #define NPCM8XX_CLK_SPI1 23 36*08e95044STomer Maimon #define NPCM8XX_CLK_SPIX 24 37*08e95044STomer Maimon #define NPCM8XX_CLK_RG 25 38*08e95044STomer Maimon #define NPCM8XX_CLK_RCP 26 39*08e95044STomer Maimon #define NPCM8XX_CLK_PRE_ADC 27 40*08e95044STomer Maimon #define NPCM8XX_CLK_ATB 28 41*08e95044STomer Maimon #define NPCM8XX_CLK_PRE_CLK 29 42*08e95044STomer Maimon #define NPCM8XX_CLK_TH 30 43*08e95044STomer Maimon #define NPCM8XX_CLK_REFCLK 31 44*08e95044STomer Maimon #define NPCM8XX_CLK_SYSBYPCK 32 45*08e95044STomer Maimon #define NPCM8XX_CLK_MCBYPCK 33 46*08e95044STomer Maimon 47*08e95044STomer Maimon #define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_MCBYPCK + 1) 48*08e95044STomer Maimon 49*08e95044STomer Maimon #endif 50