1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef _DT_BINDINGS_CLK_MT8173_H 16 #define _DT_BINDINGS_CLK_MT8173_H 17 18 /* TOPCKGEN */ 19 20 #define CLK_TOP_CLKPH_MCK_O 1 21 #define CLK_TOP_DPI 2 22 #define CLK_TOP_USB_SYSPLL_125M 3 23 #define CLK_TOP_HDMITX_DIG_CTS 4 24 #define CLK_TOP_ARMCA7PLL_754M 5 25 #define CLK_TOP_ARMCA7PLL_502M 6 26 #define CLK_TOP_MAIN_H546M 7 27 #define CLK_TOP_MAIN_H364M 8 28 #define CLK_TOP_MAIN_H218P4M 9 29 #define CLK_TOP_MAIN_H156M 10 30 #define CLK_TOP_TVDPLL_445P5M 11 31 #define CLK_TOP_TVDPLL_594M 12 32 #define CLK_TOP_UNIV_624M 13 33 #define CLK_TOP_UNIV_416M 14 34 #define CLK_TOP_UNIV_249P6M 15 35 #define CLK_TOP_UNIV_178P3M 16 36 #define CLK_TOP_UNIV_48M 17 37 #define CLK_TOP_CLKRTC_EXT 18 38 #define CLK_TOP_CLKRTC_INT 19 39 #define CLK_TOP_FPC 20 40 #define CLK_TOP_HDMITXPLL_D2 21 41 #define CLK_TOP_HDMITXPLL_D3 22 42 #define CLK_TOP_ARMCA7PLL_D2 23 43 #define CLK_TOP_ARMCA7PLL_D3 24 44 #define CLK_TOP_APLL1 25 45 #define CLK_TOP_APLL2 26 46 #define CLK_TOP_DMPLL 27 47 #define CLK_TOP_DMPLL_D2 28 48 #define CLK_TOP_DMPLL_D4 29 49 #define CLK_TOP_DMPLL_D8 30 50 #define CLK_TOP_DMPLL_D16 31 51 #define CLK_TOP_LVDSPLL_D2 32 52 #define CLK_TOP_LVDSPLL_D4 33 53 #define CLK_TOP_LVDSPLL_D8 34 54 #define CLK_TOP_MMPLL 35 55 #define CLK_TOP_MMPLL_D2 36 56 #define CLK_TOP_MSDCPLL 37 57 #define CLK_TOP_MSDCPLL_D2 38 58 #define CLK_TOP_MSDCPLL_D4 39 59 #define CLK_TOP_MSDCPLL2 40 60 #define CLK_TOP_MSDCPLL2_D2 41 61 #define CLK_TOP_MSDCPLL2_D4 42 62 #define CLK_TOP_SYSPLL_D2 43 63 #define CLK_TOP_SYSPLL1_D2 44 64 #define CLK_TOP_SYSPLL1_D4 45 65 #define CLK_TOP_SYSPLL1_D8 46 66 #define CLK_TOP_SYSPLL1_D16 47 67 #define CLK_TOP_SYSPLL_D3 48 68 #define CLK_TOP_SYSPLL2_D2 49 69 #define CLK_TOP_SYSPLL2_D4 50 70 #define CLK_TOP_SYSPLL_D5 51 71 #define CLK_TOP_SYSPLL3_D2 52 72 #define CLK_TOP_SYSPLL3_D4 53 73 #define CLK_TOP_SYSPLL_D7 54 74 #define CLK_TOP_SYSPLL4_D2 55 75 #define CLK_TOP_SYSPLL4_D4 56 76 #define CLK_TOP_TVDPLL 57 77 #define CLK_TOP_TVDPLL_D2 58 78 #define CLK_TOP_TVDPLL_D4 59 79 #define CLK_TOP_TVDPLL_D8 60 80 #define CLK_TOP_TVDPLL_D16 61 81 #define CLK_TOP_UNIVPLL_D2 62 82 #define CLK_TOP_UNIVPLL1_D2 63 83 #define CLK_TOP_UNIVPLL1_D4 64 84 #define CLK_TOP_UNIVPLL1_D8 65 85 #define CLK_TOP_UNIVPLL_D3 66 86 #define CLK_TOP_UNIVPLL2_D2 67 87 #define CLK_TOP_UNIVPLL2_D4 68 88 #define CLK_TOP_UNIVPLL2_D8 69 89 #define CLK_TOP_UNIVPLL_D5 70 90 #define CLK_TOP_UNIVPLL3_D2 71 91 #define CLK_TOP_UNIVPLL3_D4 72 92 #define CLK_TOP_UNIVPLL3_D8 73 93 #define CLK_TOP_UNIVPLL_D7 74 94 #define CLK_TOP_UNIVPLL_D26 75 95 #define CLK_TOP_UNIVPLL_D52 76 96 #define CLK_TOP_VCODECPLL 77 97 #define CLK_TOP_VCODECPLL_370P5 78 98 #define CLK_TOP_VENCPLL 79 99 #define CLK_TOP_VENCPLL_D2 80 100 #define CLK_TOP_VENCPLL_D4 81 101 #define CLK_TOP_AXI_SEL 82 102 #define CLK_TOP_MEM_SEL 83 103 #define CLK_TOP_DDRPHYCFG_SEL 84 104 #define CLK_TOP_MM_SEL 85 105 #define CLK_TOP_PWM_SEL 86 106 #define CLK_TOP_VDEC_SEL 87 107 #define CLK_TOP_VENC_SEL 88 108 #define CLK_TOP_MFG_SEL 89 109 #define CLK_TOP_CAMTG_SEL 90 110 #define CLK_TOP_UART_SEL 91 111 #define CLK_TOP_SPI_SEL 92 112 #define CLK_TOP_USB20_SEL 93 113 #define CLK_TOP_USB30_SEL 94 114 #define CLK_TOP_MSDC50_0_H_SEL 95 115 #define CLK_TOP_MSDC50_0_SEL 96 116 #define CLK_TOP_MSDC30_1_SEL 97 117 #define CLK_TOP_MSDC30_2_SEL 98 118 #define CLK_TOP_MSDC30_3_SEL 99 119 #define CLK_TOP_AUDIO_SEL 100 120 #define CLK_TOP_AUD_INTBUS_SEL 101 121 #define CLK_TOP_PMICSPI_SEL 102 122 #define CLK_TOP_SCP_SEL 103 123 #define CLK_TOP_ATB_SEL 104 124 #define CLK_TOP_VENC_LT_SEL 105 125 #define CLK_TOP_DPI0_SEL 106 126 #define CLK_TOP_IRDA_SEL 107 127 #define CLK_TOP_CCI400_SEL 108 128 #define CLK_TOP_AUD_1_SEL 109 129 #define CLK_TOP_AUD_2_SEL 110 130 #define CLK_TOP_MEM_MFG_IN_SEL 111 131 #define CLK_TOP_AXI_MFG_IN_SEL 112 132 #define CLK_TOP_SCAM_SEL 113 133 #define CLK_TOP_SPINFI_IFR_SEL 114 134 #define CLK_TOP_HDMI_SEL 115 135 #define CLK_TOP_DPILVDS_SEL 116 136 #define CLK_TOP_MSDC50_2_H_SEL 117 137 #define CLK_TOP_HDCP_SEL 118 138 #define CLK_TOP_HDCP_24M_SEL 119 139 #define CLK_TOP_RTC_SEL 120 140 #define CLK_TOP_APLL1_DIV0 121 141 #define CLK_TOP_APLL1_DIV1 122 142 #define CLK_TOP_APLL1_DIV2 123 143 #define CLK_TOP_APLL1_DIV3 124 144 #define CLK_TOP_APLL1_DIV4 125 145 #define CLK_TOP_APLL1_DIV5 126 146 #define CLK_TOP_APLL2_DIV0 127 147 #define CLK_TOP_APLL2_DIV1 128 148 #define CLK_TOP_APLL2_DIV2 129 149 #define CLK_TOP_APLL2_DIV3 130 150 #define CLK_TOP_APLL2_DIV4 131 151 #define CLK_TOP_APLL2_DIV5 132 152 #define CLK_TOP_I2S0_M_SEL 133 153 #define CLK_TOP_I2S1_M_SEL 134 154 #define CLK_TOP_I2S2_M_SEL 135 155 #define CLK_TOP_I2S3_M_SEL 136 156 #define CLK_TOP_I2S3_B_SEL 137 157 #define CLK_TOP_NR_CLK 138 158 159 /* APMIXED_SYS */ 160 161 #define CLK_APMIXED_ARMCA15PLL 1 162 #define CLK_APMIXED_ARMCA7PLL 2 163 #define CLK_APMIXED_MAINPLL 3 164 #define CLK_APMIXED_UNIVPLL 4 165 #define CLK_APMIXED_MMPLL 5 166 #define CLK_APMIXED_MSDCPLL 6 167 #define CLK_APMIXED_VENCPLL 7 168 #define CLK_APMIXED_TVDPLL 8 169 #define CLK_APMIXED_MPLL 9 170 #define CLK_APMIXED_VCODECPLL 10 171 #define CLK_APMIXED_APLL1 11 172 #define CLK_APMIXED_APLL2 12 173 #define CLK_APMIXED_LVDSPLL 13 174 #define CLK_APMIXED_MSDCPLL2 14 175 #define CLK_APMIXED_NR_CLK 15 176 177 /* INFRA_SYS */ 178 179 #define CLK_INFRA_DBGCLK 1 180 #define CLK_INFRA_SMI 2 181 #define CLK_INFRA_AUDIO 3 182 #define CLK_INFRA_GCE 4 183 #define CLK_INFRA_L2C_SRAM 5 184 #define CLK_INFRA_M4U 6 185 #define CLK_INFRA_CPUM 7 186 #define CLK_INFRA_KP 8 187 #define CLK_INFRA_CEC 9 188 #define CLK_INFRA_PMICSPI 10 189 #define CLK_INFRA_PMICWRAP 11 190 #define CLK_INFRA_NR_CLK 12 191 192 /* PERI_SYS */ 193 194 #define CLK_PERI_NFI 1 195 #define CLK_PERI_THERM 2 196 #define CLK_PERI_PWM1 3 197 #define CLK_PERI_PWM2 4 198 #define CLK_PERI_PWM3 5 199 #define CLK_PERI_PWM4 6 200 #define CLK_PERI_PWM5 7 201 #define CLK_PERI_PWM6 8 202 #define CLK_PERI_PWM7 9 203 #define CLK_PERI_PWM 10 204 #define CLK_PERI_USB0 11 205 #define CLK_PERI_USB1 12 206 #define CLK_PERI_AP_DMA 13 207 #define CLK_PERI_MSDC30_0 14 208 #define CLK_PERI_MSDC30_1 15 209 #define CLK_PERI_MSDC30_2 16 210 #define CLK_PERI_MSDC30_3 17 211 #define CLK_PERI_NLI_ARB 18 212 #define CLK_PERI_IRDA 19 213 #define CLK_PERI_UART0 20 214 #define CLK_PERI_UART1 21 215 #define CLK_PERI_UART2 22 216 #define CLK_PERI_UART3 23 217 #define CLK_PERI_I2C0 24 218 #define CLK_PERI_I2C1 25 219 #define CLK_PERI_I2C2 26 220 #define CLK_PERI_I2C3 27 221 #define CLK_PERI_I2C4 28 222 #define CLK_PERI_AUXADC 29 223 #define CLK_PERI_SPI0 30 224 #define CLK_PERI_I2C5 31 225 #define CLK_PERI_NFIECC 32 226 #define CLK_PERI_SPI 33 227 #define CLK_PERI_IRRX 34 228 #define CLK_PERI_I2C6 35 229 #define CLK_PERI_UART0_SEL 36 230 #define CLK_PERI_UART1_SEL 37 231 #define CLK_PERI_UART2_SEL 38 232 #define CLK_PERI_UART3_SEL 39 233 #define CLK_PERI_NR_CLK 40 234 235 #endif /* _DT_BINDINGS_CLK_MT8173_H */ 236