1*4cc5e1caSGerhard Sittig /* 2*4cc5e1caSGerhard Sittig * This header provides constants for MPC512x clock specs in DT bindings. 3*4cc5e1caSGerhard Sittig */ 4*4cc5e1caSGerhard Sittig 5*4cc5e1caSGerhard Sittig #ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H 6*4cc5e1caSGerhard Sittig #define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H 7*4cc5e1caSGerhard Sittig 8*4cc5e1caSGerhard Sittig #define MPC512x_CLK_DUMMY 0 9*4cc5e1caSGerhard Sittig #define MPC512x_CLK_REF 1 10*4cc5e1caSGerhard Sittig #define MPC512x_CLK_SYS 2 11*4cc5e1caSGerhard Sittig #define MPC512x_CLK_DIU 3 12*4cc5e1caSGerhard Sittig #define MPC512x_CLK_VIU 4 13*4cc5e1caSGerhard Sittig #define MPC512x_CLK_CSB 5 14*4cc5e1caSGerhard Sittig #define MPC512x_CLK_E300 6 15*4cc5e1caSGerhard Sittig #define MPC512x_CLK_IPS 7 16*4cc5e1caSGerhard Sittig #define MPC512x_CLK_FEC 8 17*4cc5e1caSGerhard Sittig #define MPC512x_CLK_SATA 9 18*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PATA 10 19*4cc5e1caSGerhard Sittig #define MPC512x_CLK_NFC 11 20*4cc5e1caSGerhard Sittig #define MPC512x_CLK_LPC 12 21*4cc5e1caSGerhard Sittig #define MPC512x_CLK_MBX_BUS 13 22*4cc5e1caSGerhard Sittig #define MPC512x_CLK_MBX 14 23*4cc5e1caSGerhard Sittig #define MPC512x_CLK_MBX_3D 15 24*4cc5e1caSGerhard Sittig #define MPC512x_CLK_AXE 16 25*4cc5e1caSGerhard Sittig #define MPC512x_CLK_USB1 17 26*4cc5e1caSGerhard Sittig #define MPC512x_CLK_USB2 18 27*4cc5e1caSGerhard Sittig #define MPC512x_CLK_I2C 19 28*4cc5e1caSGerhard Sittig #define MPC512x_CLK_MSCAN0_MCLK 20 29*4cc5e1caSGerhard Sittig #define MPC512x_CLK_MSCAN1_MCLK 21 30*4cc5e1caSGerhard Sittig #define MPC512x_CLK_MSCAN2_MCLK 22 31*4cc5e1caSGerhard Sittig #define MPC512x_CLK_MSCAN3_MCLK 23 32*4cc5e1caSGerhard Sittig #define MPC512x_CLK_BDLC 24 33*4cc5e1caSGerhard Sittig #define MPC512x_CLK_SDHC 25 34*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PCI 26 35*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC_MCLK_IN 27 36*4cc5e1caSGerhard Sittig #define MPC512x_CLK_SPDIF_TX 28 37*4cc5e1caSGerhard Sittig #define MPC512x_CLK_SPDIF_RX 29 38*4cc5e1caSGerhard Sittig #define MPC512x_CLK_SPDIF_MCLK 30 39*4cc5e1caSGerhard Sittig #define MPC512x_CLK_SPDIF 31 40*4cc5e1caSGerhard Sittig #define MPC512x_CLK_AC97 32 41*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC0_MCLK 33 42*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC1_MCLK 34 43*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC2_MCLK 35 44*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC3_MCLK 36 45*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC4_MCLK 37 46*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC5_MCLK 38 47*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC6_MCLK 39 48*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC7_MCLK 40 49*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC8_MCLK 41 50*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC9_MCLK 42 51*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC10_MCLK 43 52*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC11_MCLK 44 53*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC_FIFO 45 54*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC0 46 55*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC1 47 56*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC2 48 57*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC3 49 58*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC4 50 59*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC5 51 60*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC6 52 61*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC7 53 62*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC8 54 63*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC9 55 64*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC10 56 65*4cc5e1caSGerhard Sittig #define MPC512x_CLK_PSC11 57 66*4cc5e1caSGerhard Sittig 67*4cc5e1caSGerhard Sittig #define MPC512x_CLK_LAST_PUBLIC 57 68*4cc5e1caSGerhard Sittig 69*4cc5e1caSGerhard Sittig #endif 70