12145bb68SDaire McNamara /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 22145bb68SDaire McNamara /* 32145bb68SDaire McNamara * Daire McNamara,<daire.mcnamara@microchip.com> 48be99c7bSConor Dooley * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. 52145bb68SDaire McNamara */ 62145bb68SDaire McNamara 72145bb68SDaire McNamara #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ 82145bb68SDaire McNamara #define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ 92145bb68SDaire McNamara 102145bb68SDaire McNamara #define CLK_CPU 0 112145bb68SDaire McNamara #define CLK_AXI 1 122145bb68SDaire McNamara #define CLK_AHB 2 132145bb68SDaire McNamara 142145bb68SDaire McNamara #define CLK_ENVM 3 152145bb68SDaire McNamara #define CLK_MAC0 4 162145bb68SDaire McNamara #define CLK_MAC1 5 172145bb68SDaire McNamara #define CLK_MMC 6 182145bb68SDaire McNamara #define CLK_TIMER 7 192145bb68SDaire McNamara #define CLK_MMUART0 8 202145bb68SDaire McNamara #define CLK_MMUART1 9 212145bb68SDaire McNamara #define CLK_MMUART2 10 222145bb68SDaire McNamara #define CLK_MMUART3 11 232145bb68SDaire McNamara #define CLK_MMUART4 12 242145bb68SDaire McNamara #define CLK_SPI0 13 252145bb68SDaire McNamara #define CLK_SPI1 14 262145bb68SDaire McNamara #define CLK_I2C0 15 272145bb68SDaire McNamara #define CLK_I2C1 16 282145bb68SDaire McNamara #define CLK_CAN0 17 292145bb68SDaire McNamara #define CLK_CAN1 18 302145bb68SDaire McNamara #define CLK_USB 19 312145bb68SDaire McNamara #define CLK_RESERVED 20 322145bb68SDaire McNamara #define CLK_RTC 21 332145bb68SDaire McNamara #define CLK_QSPI 22 342145bb68SDaire McNamara #define CLK_GPIO0 23 352145bb68SDaire McNamara #define CLK_GPIO1 24 362145bb68SDaire McNamara #define CLK_GPIO2 25 372145bb68SDaire McNamara #define CLK_DDRC 26 382145bb68SDaire McNamara #define CLK_FIC0 27 392145bb68SDaire McNamara #define CLK_FIC1 28 402145bb68SDaire McNamara #define CLK_FIC2 29 412145bb68SDaire McNamara #define CLK_FIC3 30 422145bb68SDaire McNamara #define CLK_ATHENA 31 432145bb68SDaire McNamara #define CLK_CFM 32 442145bb68SDaire McNamara 458be99c7bSConor Dooley #define CLK_RTCREF 33 468be99c7bSConor Dooley #define CLK_MSSPLL 34 478be99c7bSConor Dooley 48*b4b02524SConor Dooley /* Clock Conditioning Circuitry Clock IDs */ 49*b4b02524SConor Dooley 50*b4b02524SConor Dooley #define CLK_CCC_PLL0 0 51*b4b02524SConor Dooley #define CLK_CCC_PLL1 1 52*b4b02524SConor Dooley #define CLK_CCC_DLL0 2 53*b4b02524SConor Dooley #define CLK_CCC_DLL1 3 54*b4b02524SConor Dooley 55*b4b02524SConor Dooley #define CLK_CCC_PLL0_OUT0 4 56*b4b02524SConor Dooley #define CLK_CCC_PLL0_OUT1 5 57*b4b02524SConor Dooley #define CLK_CCC_PLL0_OUT2 6 58*b4b02524SConor Dooley #define CLK_CCC_PLL0_OUT3 7 59*b4b02524SConor Dooley 60*b4b02524SConor Dooley #define CLK_CCC_PLL1_OUT0 8 61*b4b02524SConor Dooley #define CLK_CCC_PLL1_OUT1 9 62*b4b02524SConor Dooley #define CLK_CCC_PLL1_OUT2 10 63*b4b02524SConor Dooley #define CLK_CCC_PLL1_OUT3 11 64*b4b02524SConor Dooley 65*b4b02524SConor Dooley #define CLK_CCC_DLL0_OUT0 12 66*b4b02524SConor Dooley #define CLK_CCC_DLL0_OUT1 13 67*b4b02524SConor Dooley 68*b4b02524SConor Dooley #define CLK_CCC_DLL1_OUT0 14 69*b4b02524SConor Dooley #define CLK_CCC_DLL1_OUT1 15 70*b4b02524SConor Dooley 712145bb68SDaire McNamara #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ 72