1*ea1cca02SYassine Oudjana /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*ea1cca02SYassine Oudjana 3*ea1cca02SYassine Oudjana #ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H 4*ea1cca02SYassine Oudjana #define _DT_BINDINGS_CLK_MT6735_PERICFG_H 5*ea1cca02SYassine Oudjana 6*ea1cca02SYassine Oudjana #define CLK_PERI_DISP_PWM 0 7*ea1cca02SYassine Oudjana #define CLK_PERI_THERM 1 8*ea1cca02SYassine Oudjana #define CLK_PERI_PWM1 2 9*ea1cca02SYassine Oudjana #define CLK_PERI_PWM2 3 10*ea1cca02SYassine Oudjana #define CLK_PERI_PWM3 4 11*ea1cca02SYassine Oudjana #define CLK_PERI_PWM4 5 12*ea1cca02SYassine Oudjana #define CLK_PERI_PWM5 6 13*ea1cca02SYassine Oudjana #define CLK_PERI_PWM6 7 14*ea1cca02SYassine Oudjana #define CLK_PERI_PWM7 8 15*ea1cca02SYassine Oudjana #define CLK_PERI_PWM 9 16*ea1cca02SYassine Oudjana #define CLK_PERI_USB0 10 17*ea1cca02SYassine Oudjana #define CLK_PERI_IRDA 11 18*ea1cca02SYassine Oudjana #define CLK_PERI_APDMA 12 19*ea1cca02SYassine Oudjana #define CLK_PERI_MSDC30_0 13 20*ea1cca02SYassine Oudjana #define CLK_PERI_MSDC30_1 14 21*ea1cca02SYassine Oudjana #define CLK_PERI_MSDC30_2 15 22*ea1cca02SYassine Oudjana #define CLK_PERI_MSDC30_3 16 23*ea1cca02SYassine Oudjana #define CLK_PERI_UART0 17 24*ea1cca02SYassine Oudjana #define CLK_PERI_UART1 18 25*ea1cca02SYassine Oudjana #define CLK_PERI_UART2 19 26*ea1cca02SYassine Oudjana #define CLK_PERI_UART3 20 27*ea1cca02SYassine Oudjana #define CLK_PERI_UART4 21 28*ea1cca02SYassine Oudjana #define CLK_PERI_BTIF 22 29*ea1cca02SYassine Oudjana #define CLK_PERI_I2C0 23 30*ea1cca02SYassine Oudjana #define CLK_PERI_I2C1 24 31*ea1cca02SYassine Oudjana #define CLK_PERI_I2C2 25 32*ea1cca02SYassine Oudjana #define CLK_PERI_I2C3 26 33*ea1cca02SYassine Oudjana #define CLK_PERI_AUXADC 27 34*ea1cca02SYassine Oudjana #define CLK_PERI_SPI0 28 35*ea1cca02SYassine Oudjana #define CLK_PERI_IRTX 29 36*ea1cca02SYassine Oudjana 37*ea1cca02SYassine Oudjana #endif 38