11ec770d9SChao Xie #ifndef __DTS_MARVELL_MMP2_CLOCK_H 21ec770d9SChao Xie #define __DTS_MARVELL_MMP2_CLOCK_H 31ec770d9SChao Xie 41ec770d9SChao Xie /* fixed clocks and plls */ 51ec770d9SChao Xie #define MMP2_CLK_CLK32 1 61ec770d9SChao Xie #define MMP2_CLK_VCTCXO 2 71ec770d9SChao Xie #define MMP2_CLK_PLL1 3 81ec770d9SChao Xie #define MMP2_CLK_PLL1_2 8 91ec770d9SChao Xie #define MMP2_CLK_PLL1_4 9 101ec770d9SChao Xie #define MMP2_CLK_PLL1_8 10 111ec770d9SChao Xie #define MMP2_CLK_PLL1_16 11 121ec770d9SChao Xie #define MMP2_CLK_PLL1_3 12 131ec770d9SChao Xie #define MMP2_CLK_PLL1_6 13 141ec770d9SChao Xie #define MMP2_CLK_PLL1_12 14 151ec770d9SChao Xie #define MMP2_CLK_PLL1_20 15 161ec770d9SChao Xie #define MMP2_CLK_PLL2 16 171ec770d9SChao Xie #define MMP2_CLK_PLL2_2 17 181ec770d9SChao Xie #define MMP2_CLK_PLL2_4 18 191ec770d9SChao Xie #define MMP2_CLK_PLL2_8 19 201ec770d9SChao Xie #define MMP2_CLK_PLL2_16 20 211ec770d9SChao Xie #define MMP2_CLK_PLL2_3 21 221ec770d9SChao Xie #define MMP2_CLK_PLL2_6 22 231ec770d9SChao Xie #define MMP2_CLK_PLL2_12 23 241ec770d9SChao Xie #define MMP2_CLK_VCTCXO_2 24 251ec770d9SChao Xie #define MMP2_CLK_VCTCXO_4 25 261ec770d9SChao Xie #define MMP2_CLK_UART_PLL 26 271ec770d9SChao Xie #define MMP2_CLK_USB_PLL 27 281ec770d9SChao Xie 291ec770d9SChao Xie /* apb periphrals */ 301ec770d9SChao Xie #define MMP2_CLK_TWSI0 60 311ec770d9SChao Xie #define MMP2_CLK_TWSI1 61 321ec770d9SChao Xie #define MMP2_CLK_TWSI2 62 331ec770d9SChao Xie #define MMP2_CLK_TWSI3 63 341ec770d9SChao Xie #define MMP2_CLK_TWSI4 64 351ec770d9SChao Xie #define MMP2_CLK_TWSI5 65 361ec770d9SChao Xie #define MMP2_CLK_GPIO 66 371ec770d9SChao Xie #define MMP2_CLK_KPC 67 381ec770d9SChao Xie #define MMP2_CLK_RTC 68 391ec770d9SChao Xie #define MMP2_CLK_PWM0 69 401ec770d9SChao Xie #define MMP2_CLK_PWM1 70 411ec770d9SChao Xie #define MMP2_CLK_PWM2 71 421ec770d9SChao Xie #define MMP2_CLK_PWM3 72 431ec770d9SChao Xie #define MMP2_CLK_UART0 73 441ec770d9SChao Xie #define MMP2_CLK_UART1 74 451ec770d9SChao Xie #define MMP2_CLK_UART2 75 461ec770d9SChao Xie #define MMP2_CLK_UART3 76 471ec770d9SChao Xie #define MMP2_CLK_SSP0 77 481ec770d9SChao Xie #define MMP2_CLK_SSP1 78 491ec770d9SChao Xie #define MMP2_CLK_SSP2 79 501ec770d9SChao Xie #define MMP2_CLK_SSP3 80 51*24c65a02SChao Xie #define MMP2_CLK_TIMER 81 521ec770d9SChao Xie 531ec770d9SChao Xie /* axi periphrals */ 541ec770d9SChao Xie #define MMP2_CLK_SDH0 101 551ec770d9SChao Xie #define MMP2_CLK_SDH1 102 561ec770d9SChao Xie #define MMP2_CLK_SDH2 103 571ec770d9SChao Xie #define MMP2_CLK_SDH3 104 581ec770d9SChao Xie #define MMP2_CLK_USB 105 591ec770d9SChao Xie #define MMP2_CLK_DISP0 106 601ec770d9SChao Xie #define MMP2_CLK_DISP0_MUX 107 611ec770d9SChao Xie #define MMP2_CLK_DISP0_SPHY 108 621ec770d9SChao Xie #define MMP2_CLK_DISP1 109 631ec770d9SChao Xie #define MMP2_CLK_DISP1_MUX 110 641ec770d9SChao Xie #define MMP2_CLK_CCIC_ARBITER 111 651ec770d9SChao Xie #define MMP2_CLK_CCIC0 112 661ec770d9SChao Xie #define MMP2_CLK_CCIC0_MIX 113 671ec770d9SChao Xie #define MMP2_CLK_CCIC0_PHY 114 681ec770d9SChao Xie #define MMP2_CLK_CCIC0_SPHY 115 691ec770d9SChao Xie #define MMP2_CLK_CCIC1 116 701ec770d9SChao Xie #define MMP2_CLK_CCIC1_MIX 117 711ec770d9SChao Xie #define MMP2_CLK_CCIC1_PHY 118 721ec770d9SChao Xie #define MMP2_CLK_CCIC1_SPHY 119 731ec770d9SChao Xie 741ec770d9SChao Xie #define MMP2_NR_CLKS 200 751ec770d9SChao Xie #endif 76