1*1ec770d9SChao Xie #ifndef __DTS_MARVELL_MMP2_CLOCK_H 2*1ec770d9SChao Xie #define __DTS_MARVELL_MMP2_CLOCK_H 3*1ec770d9SChao Xie 4*1ec770d9SChao Xie /* fixed clocks and plls */ 5*1ec770d9SChao Xie #define MMP2_CLK_CLK32 1 6*1ec770d9SChao Xie #define MMP2_CLK_VCTCXO 2 7*1ec770d9SChao Xie #define MMP2_CLK_PLL1 3 8*1ec770d9SChao Xie #define MMP2_CLK_PLL1_2 8 9*1ec770d9SChao Xie #define MMP2_CLK_PLL1_4 9 10*1ec770d9SChao Xie #define MMP2_CLK_PLL1_8 10 11*1ec770d9SChao Xie #define MMP2_CLK_PLL1_16 11 12*1ec770d9SChao Xie #define MMP2_CLK_PLL1_3 12 13*1ec770d9SChao Xie #define MMP2_CLK_PLL1_6 13 14*1ec770d9SChao Xie #define MMP2_CLK_PLL1_12 14 15*1ec770d9SChao Xie #define MMP2_CLK_PLL1_20 15 16*1ec770d9SChao Xie #define MMP2_CLK_PLL2 16 17*1ec770d9SChao Xie #define MMP2_CLK_PLL2_2 17 18*1ec770d9SChao Xie #define MMP2_CLK_PLL2_4 18 19*1ec770d9SChao Xie #define MMP2_CLK_PLL2_8 19 20*1ec770d9SChao Xie #define MMP2_CLK_PLL2_16 20 21*1ec770d9SChao Xie #define MMP2_CLK_PLL2_3 21 22*1ec770d9SChao Xie #define MMP2_CLK_PLL2_6 22 23*1ec770d9SChao Xie #define MMP2_CLK_PLL2_12 23 24*1ec770d9SChao Xie #define MMP2_CLK_VCTCXO_2 24 25*1ec770d9SChao Xie #define MMP2_CLK_VCTCXO_4 25 26*1ec770d9SChao Xie #define MMP2_CLK_UART_PLL 26 27*1ec770d9SChao Xie #define MMP2_CLK_USB_PLL 27 28*1ec770d9SChao Xie 29*1ec770d9SChao Xie /* apb periphrals */ 30*1ec770d9SChao Xie #define MMP2_CLK_TWSI0 60 31*1ec770d9SChao Xie #define MMP2_CLK_TWSI1 61 32*1ec770d9SChao Xie #define MMP2_CLK_TWSI2 62 33*1ec770d9SChao Xie #define MMP2_CLK_TWSI3 63 34*1ec770d9SChao Xie #define MMP2_CLK_TWSI4 64 35*1ec770d9SChao Xie #define MMP2_CLK_TWSI5 65 36*1ec770d9SChao Xie #define MMP2_CLK_GPIO 66 37*1ec770d9SChao Xie #define MMP2_CLK_KPC 67 38*1ec770d9SChao Xie #define MMP2_CLK_RTC 68 39*1ec770d9SChao Xie #define MMP2_CLK_PWM0 69 40*1ec770d9SChao Xie #define MMP2_CLK_PWM1 70 41*1ec770d9SChao Xie #define MMP2_CLK_PWM2 71 42*1ec770d9SChao Xie #define MMP2_CLK_PWM3 72 43*1ec770d9SChao Xie #define MMP2_CLK_UART0 73 44*1ec770d9SChao Xie #define MMP2_CLK_UART1 74 45*1ec770d9SChao Xie #define MMP2_CLK_UART2 75 46*1ec770d9SChao Xie #define MMP2_CLK_UART3 76 47*1ec770d9SChao Xie #define MMP2_CLK_SSP0 77 48*1ec770d9SChao Xie #define MMP2_CLK_SSP1 78 49*1ec770d9SChao Xie #define MMP2_CLK_SSP2 79 50*1ec770d9SChao Xie #define MMP2_CLK_SSP3 80 51*1ec770d9SChao Xie 52*1ec770d9SChao Xie /* axi periphrals */ 53*1ec770d9SChao Xie #define MMP2_CLK_SDH0 101 54*1ec770d9SChao Xie #define MMP2_CLK_SDH1 102 55*1ec770d9SChao Xie #define MMP2_CLK_SDH2 103 56*1ec770d9SChao Xie #define MMP2_CLK_SDH3 104 57*1ec770d9SChao Xie #define MMP2_CLK_USB 105 58*1ec770d9SChao Xie #define MMP2_CLK_DISP0 106 59*1ec770d9SChao Xie #define MMP2_CLK_DISP0_MUX 107 60*1ec770d9SChao Xie #define MMP2_CLK_DISP0_SPHY 108 61*1ec770d9SChao Xie #define MMP2_CLK_DISP1 109 62*1ec770d9SChao Xie #define MMP2_CLK_DISP1_MUX 110 63*1ec770d9SChao Xie #define MMP2_CLK_CCIC_ARBITER 111 64*1ec770d9SChao Xie #define MMP2_CLK_CCIC0 112 65*1ec770d9SChao Xie #define MMP2_CLK_CCIC0_MIX 113 66*1ec770d9SChao Xie #define MMP2_CLK_CCIC0_PHY 114 67*1ec770d9SChao Xie #define MMP2_CLK_CCIC0_SPHY 115 68*1ec770d9SChao Xie #define MMP2_CLK_CCIC1 116 69*1ec770d9SChao Xie #define MMP2_CLK_CCIC1_MIX 117 70*1ec770d9SChao Xie #define MMP2_CLK_CCIC1_PHY 118 71*1ec770d9SChao Xie #define MMP2_CLK_CCIC1_SPHY 119 72*1ec770d9SChao Xie 73*1ec770d9SChao Xie #define MMP2_NR_CLKS 200 74*1ec770d9SChao Xie #endif 75