xref: /linux/include/dt-bindings/clock/marvell,mmp2.h (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
21ec770d9SChao Xie #ifndef __DTS_MARVELL_MMP2_CLOCK_H
31ec770d9SChao Xie #define __DTS_MARVELL_MMP2_CLOCK_H
41ec770d9SChao Xie 
51ec770d9SChao Xie /* fixed clocks and plls */
61ec770d9SChao Xie #define MMP2_CLK_CLK32			1
71ec770d9SChao Xie #define MMP2_CLK_VCTCXO			2
81ec770d9SChao Xie #define MMP2_CLK_PLL1			3
91ec770d9SChao Xie #define MMP2_CLK_PLL1_2			8
101ec770d9SChao Xie #define MMP2_CLK_PLL1_4			9
111ec770d9SChao Xie #define MMP2_CLK_PLL1_8			10
121ec770d9SChao Xie #define MMP2_CLK_PLL1_16		11
131ec770d9SChao Xie #define MMP2_CLK_PLL1_3			12
141ec770d9SChao Xie #define MMP2_CLK_PLL1_6			13
151ec770d9SChao Xie #define MMP2_CLK_PLL1_12		14
161ec770d9SChao Xie #define MMP2_CLK_PLL1_20		15
171ec770d9SChao Xie #define MMP2_CLK_PLL2			16
181ec770d9SChao Xie #define MMP2_CLK_PLL2_2			17
191ec770d9SChao Xie #define MMP2_CLK_PLL2_4			18
201ec770d9SChao Xie #define MMP2_CLK_PLL2_8			19
211ec770d9SChao Xie #define MMP2_CLK_PLL2_16		20
221ec770d9SChao Xie #define MMP2_CLK_PLL2_3			21
231ec770d9SChao Xie #define MMP2_CLK_PLL2_6			22
241ec770d9SChao Xie #define MMP2_CLK_PLL2_12		23
251ec770d9SChao Xie #define MMP2_CLK_VCTCXO_2		24
261ec770d9SChao Xie #define MMP2_CLK_VCTCXO_4		25
271ec770d9SChao Xie #define MMP2_CLK_UART_PLL		26
281ec770d9SChao Xie #define MMP2_CLK_USB_PLL		27
294d6da655SLubomir Rintel #define MMP3_CLK_PLL1_P			28
304d6da655SLubomir Rintel #define MMP3_CLK_PLL2_P			29
314d6da655SLubomir Rintel #define MMP3_CLK_PLL3			30
32edcec4a8SLubomir Rintel #define MMP2_CLK_I2S0			31
33edcec4a8SLubomir Rintel #define MMP2_CLK_I2S1			32
341ec770d9SChao Xie 
35*6853feceSTom Rix /* apb peripherals */
361ec770d9SChao Xie #define MMP2_CLK_TWSI0			60
371ec770d9SChao Xie #define MMP2_CLK_TWSI1			61
381ec770d9SChao Xie #define MMP2_CLK_TWSI2			62
391ec770d9SChao Xie #define MMP2_CLK_TWSI3			63
401ec770d9SChao Xie #define MMP2_CLK_TWSI4			64
411ec770d9SChao Xie #define MMP2_CLK_TWSI5			65
421ec770d9SChao Xie #define MMP2_CLK_GPIO			66
431ec770d9SChao Xie #define MMP2_CLK_KPC			67
441ec770d9SChao Xie #define MMP2_CLK_RTC			68
451ec770d9SChao Xie #define MMP2_CLK_PWM0			69
461ec770d9SChao Xie #define MMP2_CLK_PWM1			70
471ec770d9SChao Xie #define MMP2_CLK_PWM2			71
481ec770d9SChao Xie #define MMP2_CLK_PWM3			72
491ec770d9SChao Xie #define MMP2_CLK_UART0			73
501ec770d9SChao Xie #define MMP2_CLK_UART1			74
511ec770d9SChao Xie #define MMP2_CLK_UART2			75
521ec770d9SChao Xie #define MMP2_CLK_UART3			76
531ec770d9SChao Xie #define MMP2_CLK_SSP0			77
541ec770d9SChao Xie #define MMP2_CLK_SSP1			78
551ec770d9SChao Xie #define MMP2_CLK_SSP2			79
561ec770d9SChao Xie #define MMP2_CLK_SSP3			80
5724c65a02SChao Xie #define MMP2_CLK_TIMER			81
5841a86320SLubomir Rintel #define MMP2_CLK_THERMAL0		82
5941a86320SLubomir Rintel #define MMP3_CLK_THERMAL1		83
6041a86320SLubomir Rintel #define MMP3_CLK_THERMAL2		84
6141a86320SLubomir Rintel #define MMP3_CLK_THERMAL3		85
621ec770d9SChao Xie 
63*6853feceSTom Rix /* axi peripherals */
641ec770d9SChao Xie #define MMP2_CLK_SDH0			101
651ec770d9SChao Xie #define MMP2_CLK_SDH1			102
661ec770d9SChao Xie #define MMP2_CLK_SDH2			103
671ec770d9SChao Xie #define MMP2_CLK_SDH3			104
681ec770d9SChao Xie #define MMP2_CLK_USB			105
691ec770d9SChao Xie #define MMP2_CLK_DISP0			106
701ec770d9SChao Xie #define MMP2_CLK_DISP0_MUX		107
711ec770d9SChao Xie #define MMP2_CLK_DISP0_SPHY		108
721ec770d9SChao Xie #define MMP2_CLK_DISP1			109
731ec770d9SChao Xie #define MMP2_CLK_DISP1_MUX		110
741ec770d9SChao Xie #define MMP2_CLK_CCIC_ARBITER		111
751ec770d9SChao Xie #define MMP2_CLK_CCIC0			112
761ec770d9SChao Xie #define MMP2_CLK_CCIC0_MIX		113
771ec770d9SChao Xie #define MMP2_CLK_CCIC0_PHY		114
781ec770d9SChao Xie #define MMP2_CLK_CCIC0_SPHY		115
791ec770d9SChao Xie #define MMP2_CLK_CCIC1			116
801ec770d9SChao Xie #define MMP2_CLK_CCIC1_MIX		117
811ec770d9SChao Xie #define MMP2_CLK_CCIC1_PHY		118
821ec770d9SChao Xie #define MMP2_CLK_CCIC1_SPHY		119
83ed11aff3SLubomir Rintel #define MMP2_CLK_DISP0_LCDC		120
84247aa9e4SLubomir Rintel #define MMP2_CLK_USBHSIC0		121
85247aa9e4SLubomir Rintel #define MMP2_CLK_USBHSIC1		122
86e3142226SLubomir Rintel #define MMP2_CLK_GPU_BUS		123
87e3142226SLubomir Rintel #define MMP3_CLK_GPU_BUS		MMP2_CLK_GPU_BUS
88e3142226SLubomir Rintel #define MMP2_CLK_GPU_3D			124
89e3142226SLubomir Rintel #define MMP3_CLK_GPU_3D			MMP2_CLK_GPU_3D
90e3142226SLubomir Rintel #define MMP3_CLK_GPU_2D			125
91c2ca122aSLubomir Rintel #define MMP3_CLK_SDH4			126
92c227df7aSLubomir Rintel #define MMP2_CLK_AUDIO			127
931ec770d9SChao Xie 
941ec770d9SChao Xie #endif
95