1*c4a11bf4SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */ 2*c4a11bf4SPaul Cercueil /* 3*c4a11bf4SPaul Cercueil * This header provides clock numbers for the ingenic,x1830-cgu DT binding. 4*c4a11bf4SPaul Cercueil * 5*c4a11bf4SPaul Cercueil * They are roughly ordered as: 6*c4a11bf4SPaul Cercueil * - external clocks 7*c4a11bf4SPaul Cercueil * - PLLs 8*c4a11bf4SPaul Cercueil * - muxes/dividers in the order they appear in the x1830 programmers manual 9*c4a11bf4SPaul Cercueil * - gates in order of their bit in the CLKGR* registers 10*c4a11bf4SPaul Cercueil */ 11*c4a11bf4SPaul Cercueil 12*c4a11bf4SPaul Cercueil #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ 13*c4a11bf4SPaul Cercueil #define __DT_BINDINGS_CLOCK_X1830_CGU_H__ 14*c4a11bf4SPaul Cercueil 15*c4a11bf4SPaul Cercueil #define X1830_CLK_EXCLK 0 16*c4a11bf4SPaul Cercueil #define X1830_CLK_RTCLK 1 17*c4a11bf4SPaul Cercueil #define X1830_CLK_APLL 2 18*c4a11bf4SPaul Cercueil #define X1830_CLK_MPLL 3 19*c4a11bf4SPaul Cercueil #define X1830_CLK_EPLL 4 20*c4a11bf4SPaul Cercueil #define X1830_CLK_VPLL 5 21*c4a11bf4SPaul Cercueil #define X1830_CLK_OTGPHY 6 22*c4a11bf4SPaul Cercueil #define X1830_CLK_SCLKA 7 23*c4a11bf4SPaul Cercueil #define X1830_CLK_CPUMUX 8 24*c4a11bf4SPaul Cercueil #define X1830_CLK_CPU 9 25*c4a11bf4SPaul Cercueil #define X1830_CLK_L2CACHE 10 26*c4a11bf4SPaul Cercueil #define X1830_CLK_AHB0 11 27*c4a11bf4SPaul Cercueil #define X1830_CLK_AHB2PMUX 12 28*c4a11bf4SPaul Cercueil #define X1830_CLK_AHB2 13 29*c4a11bf4SPaul Cercueil #define X1830_CLK_PCLK 14 30*c4a11bf4SPaul Cercueil #define X1830_CLK_DDR 15 31*c4a11bf4SPaul Cercueil #define X1830_CLK_MAC 16 32*c4a11bf4SPaul Cercueil #define X1830_CLK_LCD 17 33*c4a11bf4SPaul Cercueil #define X1830_CLK_MSCMUX 18 34*c4a11bf4SPaul Cercueil #define X1830_CLK_MSC0 19 35*c4a11bf4SPaul Cercueil #define X1830_CLK_MSC1 20 36*c4a11bf4SPaul Cercueil #define X1830_CLK_SSIPLL 21 37*c4a11bf4SPaul Cercueil #define X1830_CLK_SSIPLL_DIV2 22 38*c4a11bf4SPaul Cercueil #define X1830_CLK_SSIMUX 23 39*c4a11bf4SPaul Cercueil #define X1830_CLK_EMC 24 40*c4a11bf4SPaul Cercueil #define X1830_CLK_EFUSE 25 41*c4a11bf4SPaul Cercueil #define X1830_CLK_OTG 26 42*c4a11bf4SPaul Cercueil #define X1830_CLK_SSI0 27 43*c4a11bf4SPaul Cercueil #define X1830_CLK_SMB0 28 44*c4a11bf4SPaul Cercueil #define X1830_CLK_SMB1 29 45*c4a11bf4SPaul Cercueil #define X1830_CLK_SMB2 30 46*c4a11bf4SPaul Cercueil #define X1830_CLK_UART0 31 47*c4a11bf4SPaul Cercueil #define X1830_CLK_UART1 32 48*c4a11bf4SPaul Cercueil #define X1830_CLK_SSI1 33 49*c4a11bf4SPaul Cercueil #define X1830_CLK_SFC 34 50*c4a11bf4SPaul Cercueil #define X1830_CLK_PDMA 35 51*c4a11bf4SPaul Cercueil #define X1830_CLK_TCU 36 52*c4a11bf4SPaul Cercueil #define X1830_CLK_DTRNG 37 53*c4a11bf4SPaul Cercueil #define X1830_CLK_OST 38 54*c4a11bf4SPaul Cercueil #define X1830_CLK_EXCLK_DIV512 39 55*c4a11bf4SPaul Cercueil #define X1830_CLK_RTC 40 56*c4a11bf4SPaul Cercueil 57*c4a11bf4SPaul Cercueil #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ 58