1*c4a11bf4SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */ 2*c4a11bf4SPaul Cercueil /* 3*c4a11bf4SPaul Cercueil * This header provides clock numbers for the ingenic,x1000-cgu DT binding. 4*c4a11bf4SPaul Cercueil * 5*c4a11bf4SPaul Cercueil * They are roughly ordered as: 6*c4a11bf4SPaul Cercueil * - external clocks 7*c4a11bf4SPaul Cercueil * - PLLs 8*c4a11bf4SPaul Cercueil * - muxes/dividers in the order they appear in the x1000 programmers manual 9*c4a11bf4SPaul Cercueil * - gates in order of their bit in the CLKGR* registers 10*c4a11bf4SPaul Cercueil */ 11*c4a11bf4SPaul Cercueil 12*c4a11bf4SPaul Cercueil #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ 13*c4a11bf4SPaul Cercueil #define __DT_BINDINGS_CLOCK_X1000_CGU_H__ 14*c4a11bf4SPaul Cercueil 15*c4a11bf4SPaul Cercueil #define X1000_CLK_EXCLK 0 16*c4a11bf4SPaul Cercueil #define X1000_CLK_RTCLK 1 17*c4a11bf4SPaul Cercueil #define X1000_CLK_APLL 2 18*c4a11bf4SPaul Cercueil #define X1000_CLK_MPLL 3 19*c4a11bf4SPaul Cercueil #define X1000_CLK_OTGPHY 4 20*c4a11bf4SPaul Cercueil #define X1000_CLK_SCLKA 5 21*c4a11bf4SPaul Cercueil #define X1000_CLK_CPUMUX 6 22*c4a11bf4SPaul Cercueil #define X1000_CLK_CPU 7 23*c4a11bf4SPaul Cercueil #define X1000_CLK_L2CACHE 8 24*c4a11bf4SPaul Cercueil #define X1000_CLK_AHB0 9 25*c4a11bf4SPaul Cercueil #define X1000_CLK_AHB2PMUX 10 26*c4a11bf4SPaul Cercueil #define X1000_CLK_AHB2 11 27*c4a11bf4SPaul Cercueil #define X1000_CLK_PCLK 12 28*c4a11bf4SPaul Cercueil #define X1000_CLK_DDR 13 29*c4a11bf4SPaul Cercueil #define X1000_CLK_MAC 14 30*c4a11bf4SPaul Cercueil #define X1000_CLK_LCD 15 31*c4a11bf4SPaul Cercueil #define X1000_CLK_MSCMUX 16 32*c4a11bf4SPaul Cercueil #define X1000_CLK_MSC0 17 33*c4a11bf4SPaul Cercueil #define X1000_CLK_MSC1 18 34*c4a11bf4SPaul Cercueil #define X1000_CLK_OTG 19 35*c4a11bf4SPaul Cercueil #define X1000_CLK_SSIPLL 20 36*c4a11bf4SPaul Cercueil #define X1000_CLK_SSIPLL_DIV2 21 37*c4a11bf4SPaul Cercueil #define X1000_CLK_SSIMUX 22 38*c4a11bf4SPaul Cercueil #define X1000_CLK_EMC 23 39*c4a11bf4SPaul Cercueil #define X1000_CLK_EFUSE 24 40*c4a11bf4SPaul Cercueil #define X1000_CLK_SFC 25 41*c4a11bf4SPaul Cercueil #define X1000_CLK_I2C0 26 42*c4a11bf4SPaul Cercueil #define X1000_CLK_I2C1 27 43*c4a11bf4SPaul Cercueil #define X1000_CLK_I2C2 28 44*c4a11bf4SPaul Cercueil #define X1000_CLK_UART0 29 45*c4a11bf4SPaul Cercueil #define X1000_CLK_UART1 30 46*c4a11bf4SPaul Cercueil #define X1000_CLK_UART2 31 47*c4a11bf4SPaul Cercueil #define X1000_CLK_TCU 32 48*c4a11bf4SPaul Cercueil #define X1000_CLK_SSI 33 49*c4a11bf4SPaul Cercueil #define X1000_CLK_OST 34 50*c4a11bf4SPaul Cercueil #define X1000_CLK_PDMA 35 51*c4a11bf4SPaul Cercueil #define X1000_CLK_EXCLK_DIV512 36 52*c4a11bf4SPaul Cercueil #define X1000_CLK_RTC 37 53*c4a11bf4SPaul Cercueil 54*c4a11bf4SPaul Cercueil #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ 55