xref: /linux/include/dt-bindings/clock/ingenic,x1000-cgu.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1c4a11bf4SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */
2c4a11bf4SPaul Cercueil /*
3c4a11bf4SPaul Cercueil  * This header provides clock numbers for the ingenic,x1000-cgu DT binding.
4c4a11bf4SPaul Cercueil  *
5c4a11bf4SPaul Cercueil  * They are roughly ordered as:
6c4a11bf4SPaul Cercueil  *   - external clocks
7c4a11bf4SPaul Cercueil  *   - PLLs
8c4a11bf4SPaul Cercueil  *   - muxes/dividers in the order they appear in the x1000 programmers manual
9c4a11bf4SPaul Cercueil  *   - gates in order of their bit in the CLKGR* registers
10c4a11bf4SPaul Cercueil  */
11c4a11bf4SPaul Cercueil 
12c4a11bf4SPaul Cercueil #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
13c4a11bf4SPaul Cercueil #define __DT_BINDINGS_CLOCK_X1000_CGU_H__
14c4a11bf4SPaul Cercueil 
15c4a11bf4SPaul Cercueil #define X1000_CLK_EXCLK			0
16c4a11bf4SPaul Cercueil #define X1000_CLK_RTCLK			1
17c4a11bf4SPaul Cercueil #define X1000_CLK_APLL			2
18c4a11bf4SPaul Cercueil #define X1000_CLK_MPLL			3
19c4a11bf4SPaul Cercueil #define X1000_CLK_OTGPHY		4
20c4a11bf4SPaul Cercueil #define X1000_CLK_SCLKA			5
21c4a11bf4SPaul Cercueil #define X1000_CLK_CPUMUX		6
22c4a11bf4SPaul Cercueil #define X1000_CLK_CPU			7
23c4a11bf4SPaul Cercueil #define X1000_CLK_L2CACHE		8
24c4a11bf4SPaul Cercueil #define X1000_CLK_AHB0			9
25c4a11bf4SPaul Cercueil #define X1000_CLK_AHB2PMUX		10
26c4a11bf4SPaul Cercueil #define X1000_CLK_AHB2			11
27c4a11bf4SPaul Cercueil #define X1000_CLK_PCLK			12
28c4a11bf4SPaul Cercueil #define X1000_CLK_DDR			13
29c4a11bf4SPaul Cercueil #define X1000_CLK_MAC			14
30c4a11bf4SPaul Cercueil #define X1000_CLK_LCD			15
31c4a11bf4SPaul Cercueil #define X1000_CLK_MSCMUX		16
32c4a11bf4SPaul Cercueil #define X1000_CLK_MSC0			17
33c4a11bf4SPaul Cercueil #define X1000_CLK_MSC1			18
34c4a11bf4SPaul Cercueil #define X1000_CLK_OTG			19
35c4a11bf4SPaul Cercueil #define X1000_CLK_SSIPLL		20
36c4a11bf4SPaul Cercueil #define X1000_CLK_SSIPLL_DIV2	21
37c4a11bf4SPaul Cercueil #define X1000_CLK_SSIMUX		22
38c4a11bf4SPaul Cercueil #define X1000_CLK_EMC			23
39c4a11bf4SPaul Cercueil #define X1000_CLK_EFUSE			24
40c4a11bf4SPaul Cercueil #define X1000_CLK_SFC			25
41c4a11bf4SPaul Cercueil #define X1000_CLK_I2C0			26
42c4a11bf4SPaul Cercueil #define X1000_CLK_I2C1			27
43c4a11bf4SPaul Cercueil #define X1000_CLK_I2C2			28
44c4a11bf4SPaul Cercueil #define X1000_CLK_UART0			29
45c4a11bf4SPaul Cercueil #define X1000_CLK_UART1			30
46c4a11bf4SPaul Cercueil #define X1000_CLK_UART2			31
47c4a11bf4SPaul Cercueil #define X1000_CLK_TCU			32
48c4a11bf4SPaul Cercueil #define X1000_CLK_SSI			33
49c4a11bf4SPaul Cercueil #define X1000_CLK_OST			34
50c4a11bf4SPaul Cercueil #define X1000_CLK_PDMA			35
51c4a11bf4SPaul Cercueil #define X1000_CLK_EXCLK_DIV512	36
52c4a11bf4SPaul Cercueil #define X1000_CLK_RTC			37
53*5e5b1005SAidan MacDonald #define X1000_CLK_AIC			38
54*5e5b1005SAidan MacDonald #define X1000_CLK_I2SPLLMUX		39
55*5e5b1005SAidan MacDonald #define X1000_CLK_I2SPLL		40
56*5e5b1005SAidan MacDonald #define X1000_CLK_I2S			41
57c4a11bf4SPaul Cercueil 
58c4a11bf4SPaul Cercueil #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
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