1*c4a11bf4SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */ 2*c4a11bf4SPaul Cercueil /* 3*c4a11bf4SPaul Cercueil * This header provides clock numbers for the ingenic,jz4770-cgu DT binding. 4*c4a11bf4SPaul Cercueil */ 5*c4a11bf4SPaul Cercueil 6*c4a11bf4SPaul Cercueil #ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ 7*c4a11bf4SPaul Cercueil #define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ 8*c4a11bf4SPaul Cercueil 9*c4a11bf4SPaul Cercueil #define JZ4770_CLK_EXT 0 10*c4a11bf4SPaul Cercueil #define JZ4770_CLK_OSC32K 1 11*c4a11bf4SPaul Cercueil #define JZ4770_CLK_PLL0 2 12*c4a11bf4SPaul Cercueil #define JZ4770_CLK_PLL1 3 13*c4a11bf4SPaul Cercueil #define JZ4770_CLK_CCLK 4 14*c4a11bf4SPaul Cercueil #define JZ4770_CLK_H0CLK 5 15*c4a11bf4SPaul Cercueil #define JZ4770_CLK_H1CLK 6 16*c4a11bf4SPaul Cercueil #define JZ4770_CLK_H2CLK 7 17*c4a11bf4SPaul Cercueil #define JZ4770_CLK_C1CLK 8 18*c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCLK 9 19*c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC0_MUX 10 20*c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC0 11 21*c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC1_MUX 12 22*c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC1 13 23*c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC2_MUX 14 24*c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC2 15 25*c4a11bf4SPaul Cercueil #define JZ4770_CLK_CIM 16 26*c4a11bf4SPaul Cercueil #define JZ4770_CLK_UHC 17 27*c4a11bf4SPaul Cercueil #define JZ4770_CLK_GPU 18 28*c4a11bf4SPaul Cercueil #define JZ4770_CLK_BCH 19 29*c4a11bf4SPaul Cercueil #define JZ4770_CLK_LPCLK_MUX 20 30*c4a11bf4SPaul Cercueil #define JZ4770_CLK_GPS 21 31*c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI_MUX 22 32*c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCM_MUX 23 33*c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2S 24 34*c4a11bf4SPaul Cercueil #define JZ4770_CLK_OTG 25 35*c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI0 26 36*c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI1 27 37*c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI2 28 38*c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCM0 29 39*c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCM1 30 40*c4a11bf4SPaul Cercueil #define JZ4770_CLK_DMA 31 41*c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2C0 32 42*c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2C1 33 43*c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2C2 34 44*c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART0 35 45*c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART1 36 46*c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART2 37 47*c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART3 38 48*c4a11bf4SPaul Cercueil #define JZ4770_CLK_IPU 39 49*c4a11bf4SPaul Cercueil #define JZ4770_CLK_ADC 40 50*c4a11bf4SPaul Cercueil #define JZ4770_CLK_AIC 41 51*c4a11bf4SPaul Cercueil #define JZ4770_CLK_AUX 42 52*c4a11bf4SPaul Cercueil #define JZ4770_CLK_VPU 43 53*c4a11bf4SPaul Cercueil #define JZ4770_CLK_UHC_PHY 44 54*c4a11bf4SPaul Cercueil #define JZ4770_CLK_OTG_PHY 45 55*c4a11bf4SPaul Cercueil #define JZ4770_CLK_EXT512 46 56*c4a11bf4SPaul Cercueil #define JZ4770_CLK_RTC 47 57*c4a11bf4SPaul Cercueil 58*c4a11bf4SPaul Cercueil #endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ 59