xref: /linux/include/dt-bindings/clock/ingenic,jz4770-cgu.h (revision 51d04bcfb82a005d38b6f1011dc04a810d359aea)
1c4a11bf4SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */
2c4a11bf4SPaul Cercueil /*
3c4a11bf4SPaul Cercueil  * This header provides clock numbers for the ingenic,jz4770-cgu DT binding.
4c4a11bf4SPaul Cercueil  */
5c4a11bf4SPaul Cercueil 
6c4a11bf4SPaul Cercueil #ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
7c4a11bf4SPaul Cercueil #define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
8c4a11bf4SPaul Cercueil 
9c4a11bf4SPaul Cercueil #define JZ4770_CLK_EXT		0
10c4a11bf4SPaul Cercueil #define JZ4770_CLK_OSC32K	1
11c4a11bf4SPaul Cercueil #define JZ4770_CLK_PLL0		2
12c4a11bf4SPaul Cercueil #define JZ4770_CLK_PLL1		3
13c4a11bf4SPaul Cercueil #define JZ4770_CLK_CCLK		4
14c4a11bf4SPaul Cercueil #define JZ4770_CLK_H0CLK	5
15c4a11bf4SPaul Cercueil #define JZ4770_CLK_H1CLK	6
16c4a11bf4SPaul Cercueil #define JZ4770_CLK_H2CLK	7
17c4a11bf4SPaul Cercueil #define JZ4770_CLK_C1CLK	8
18c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCLK		9
19c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC0_MUX	10
20c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC0		11
21c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC1_MUX	12
22c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC1		13
23c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC2_MUX	14
24c4a11bf4SPaul Cercueil #define JZ4770_CLK_MMC2		15
25c4a11bf4SPaul Cercueil #define JZ4770_CLK_CIM		16
26c4a11bf4SPaul Cercueil #define JZ4770_CLK_UHC		17
27c4a11bf4SPaul Cercueil #define JZ4770_CLK_GPU		18
28c4a11bf4SPaul Cercueil #define JZ4770_CLK_BCH		19
29c4a11bf4SPaul Cercueil #define JZ4770_CLK_LPCLK_MUX	20
30c4a11bf4SPaul Cercueil #define JZ4770_CLK_GPS		21
31c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI_MUX	22
32c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCM_MUX	23
33c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2S		24
34c4a11bf4SPaul Cercueil #define JZ4770_CLK_OTG		25
35c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI0		26
36c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI1		27
37c4a11bf4SPaul Cercueil #define JZ4770_CLK_SSI2		28
38c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCM0		29
39c4a11bf4SPaul Cercueil #define JZ4770_CLK_PCM1		30
40c4a11bf4SPaul Cercueil #define JZ4770_CLK_DMA		31
41c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2C0		32
42c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2C1		33
43c4a11bf4SPaul Cercueil #define JZ4770_CLK_I2C2		34
44c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART0	35
45c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART1	36
46c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART2	37
47c4a11bf4SPaul Cercueil #define JZ4770_CLK_UART3	38
48c4a11bf4SPaul Cercueil #define JZ4770_CLK_IPU		39
49c4a11bf4SPaul Cercueil #define JZ4770_CLK_ADC		40
50c4a11bf4SPaul Cercueil #define JZ4770_CLK_AIC		41
51c4a11bf4SPaul Cercueil #define JZ4770_CLK_AUX		42
52c4a11bf4SPaul Cercueil #define JZ4770_CLK_VPU		43
53c4a11bf4SPaul Cercueil #define JZ4770_CLK_UHC_PHY	44
54c4a11bf4SPaul Cercueil #define JZ4770_CLK_OTG_PHY	45
55c4a11bf4SPaul Cercueil #define JZ4770_CLK_EXT512	46
56c4a11bf4SPaul Cercueil #define JZ4770_CLK_RTC		47
57*51d04bcfSPaul Cercueil #define JZ4770_CLK_BDMA		48
58c4a11bf4SPaul Cercueil 
59c4a11bf4SPaul Cercueil #endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */
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