1*c4a11bf4SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */ 2*c4a11bf4SPaul Cercueil /* 3*c4a11bf4SPaul Cercueil * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. 4*c4a11bf4SPaul Cercueil * 5*c4a11bf4SPaul Cercueil * They are roughly ordered as: 6*c4a11bf4SPaul Cercueil * - external clocks 7*c4a11bf4SPaul Cercueil * - PLLs 8*c4a11bf4SPaul Cercueil * - muxes/dividers in the order they appear in the jz4740 programmers manual 9*c4a11bf4SPaul Cercueil * - gates in order of their bit in the CLKGR* registers 10*c4a11bf4SPaul Cercueil */ 11*c4a11bf4SPaul Cercueil 12*c4a11bf4SPaul Cercueil #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 13*c4a11bf4SPaul Cercueil #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 14*c4a11bf4SPaul Cercueil 15*c4a11bf4SPaul Cercueil #define JZ4740_CLK_EXT 0 16*c4a11bf4SPaul Cercueil #define JZ4740_CLK_RTC 1 17*c4a11bf4SPaul Cercueil #define JZ4740_CLK_PLL 2 18*c4a11bf4SPaul Cercueil #define JZ4740_CLK_PLL_HALF 3 19*c4a11bf4SPaul Cercueil #define JZ4740_CLK_CCLK 4 20*c4a11bf4SPaul Cercueil #define JZ4740_CLK_HCLK 5 21*c4a11bf4SPaul Cercueil #define JZ4740_CLK_PCLK 6 22*c4a11bf4SPaul Cercueil #define JZ4740_CLK_MCLK 7 23*c4a11bf4SPaul Cercueil #define JZ4740_CLK_LCD 8 24*c4a11bf4SPaul Cercueil #define JZ4740_CLK_LCD_PCLK 9 25*c4a11bf4SPaul Cercueil #define JZ4740_CLK_I2S 10 26*c4a11bf4SPaul Cercueil #define JZ4740_CLK_SPI 11 27*c4a11bf4SPaul Cercueil #define JZ4740_CLK_MMC 12 28*c4a11bf4SPaul Cercueil #define JZ4740_CLK_UHC 13 29*c4a11bf4SPaul Cercueil #define JZ4740_CLK_UDC 14 30*c4a11bf4SPaul Cercueil #define JZ4740_CLK_UART0 15 31*c4a11bf4SPaul Cercueil #define JZ4740_CLK_UART1 16 32*c4a11bf4SPaul Cercueil #define JZ4740_CLK_DMA 17 33*c4a11bf4SPaul Cercueil #define JZ4740_CLK_IPU 18 34*c4a11bf4SPaul Cercueil #define JZ4740_CLK_ADC 19 35*c4a11bf4SPaul Cercueil #define JZ4740_CLK_I2C 20 36*c4a11bf4SPaul Cercueil #define JZ4740_CLK_AIC 21 37*c4a11bf4SPaul Cercueil #define JZ4740_CLK_TCU 22 38*c4a11bf4SPaul Cercueil 39*c4a11bf4SPaul Cercueil #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ 40