1*c4a11bf4SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */ 2*c4a11bf4SPaul Cercueil /* 3*c4a11bf4SPaul Cercueil * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. 4*c4a11bf4SPaul Cercueil */ 5*c4a11bf4SPaul Cercueil 6*c4a11bf4SPaul Cercueil #ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 7*c4a11bf4SPaul Cercueil #define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 8*c4a11bf4SPaul Cercueil 9*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_EXT 0 10*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_OSC32K 1 11*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_PLL 2 12*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_PLL_HALF 3 13*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_CCLK 4 14*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_HCLK 5 15*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_PCLK 6 16*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_MCLK 7 17*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_IPU 8 18*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_LCD 9 19*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_I2S 10 20*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_SPI 11 21*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_MMC_MUX 12 22*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_UDC 13 23*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_UART 14 24*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_DMA 15 25*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_ADC 16 26*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_I2C 17 27*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_AIC 18 28*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_MMC0 19 29*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_MMC1 20 30*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_BCH 21 31*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_TCU 22 32*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_EXT512 23 33*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_RTC 24 34*c4a11bf4SPaul Cercueil #define JZ4725B_CLK_UDC_PHY 25 35*c4a11bf4SPaul Cercueil 36*c4a11bf4SPaul Cercueil #endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ 37