110886914SAnson Huang /* SPDX-License-Identifier: GPL-2.0 */ 210886914SAnson Huang /* 310886914SAnson Huang * Copyright 2019 NXP 410886914SAnson Huang */ 510886914SAnson Huang 610886914SAnson Huang #ifndef __DT_BINDINGS_CLOCK_IMX8MP_H 710886914SAnson Huang #define __DT_BINDINGS_CLOCK_IMX8MP_H 810886914SAnson Huang 910886914SAnson Huang #define IMX8MP_CLK_DUMMY 0 1010886914SAnson Huang #define IMX8MP_CLK_32K 1 1110886914SAnson Huang #define IMX8MP_CLK_24M 2 1210886914SAnson Huang #define IMX8MP_OSC_HDMI_CLK 3 1310886914SAnson Huang #define IMX8MP_CLK_EXT1 4 1410886914SAnson Huang #define IMX8MP_CLK_EXT2 5 1510886914SAnson Huang #define IMX8MP_CLK_EXT3 6 1610886914SAnson Huang #define IMX8MP_CLK_EXT4 7 1710886914SAnson Huang #define IMX8MP_AUDIO_PLL1_REF_SEL 8 1810886914SAnson Huang #define IMX8MP_AUDIO_PLL2_REF_SEL 9 1910886914SAnson Huang #define IMX8MP_VIDEO_PLL1_REF_SEL 10 2010886914SAnson Huang #define IMX8MP_DRAM_PLL_REF_SEL 11 2110886914SAnson Huang #define IMX8MP_GPU_PLL_REF_SEL 12 2210886914SAnson Huang #define IMX8MP_VPU_PLL_REF_SEL 13 2310886914SAnson Huang #define IMX8MP_ARM_PLL_REF_SEL 14 2410886914SAnson Huang #define IMX8MP_SYS_PLL1_REF_SEL 15 2510886914SAnson Huang #define IMX8MP_SYS_PLL2_REF_SEL 16 2610886914SAnson Huang #define IMX8MP_SYS_PLL3_REF_SEL 17 2710886914SAnson Huang #define IMX8MP_AUDIO_PLL1 18 2810886914SAnson Huang #define IMX8MP_AUDIO_PLL2 19 2910886914SAnson Huang #define IMX8MP_VIDEO_PLL1 20 3010886914SAnson Huang #define IMX8MP_DRAM_PLL 21 3110886914SAnson Huang #define IMX8MP_GPU_PLL 22 3210886914SAnson Huang #define IMX8MP_VPU_PLL 23 3310886914SAnson Huang #define IMX8MP_ARM_PLL 24 3410886914SAnson Huang #define IMX8MP_SYS_PLL1 25 3510886914SAnson Huang #define IMX8MP_SYS_PLL2 26 3610886914SAnson Huang #define IMX8MP_SYS_PLL3 27 3710886914SAnson Huang #define IMX8MP_AUDIO_PLL1_BYPASS 28 3810886914SAnson Huang #define IMX8MP_AUDIO_PLL2_BYPASS 29 3910886914SAnson Huang #define IMX8MP_VIDEO_PLL1_BYPASS 30 4010886914SAnson Huang #define IMX8MP_DRAM_PLL_BYPASS 31 4110886914SAnson Huang #define IMX8MP_GPU_PLL_BYPASS 32 4210886914SAnson Huang #define IMX8MP_VPU_PLL_BYPASS 33 4310886914SAnson Huang #define IMX8MP_ARM_PLL_BYPASS 34 4410886914SAnson Huang #define IMX8MP_SYS_PLL1_BYPASS 35 4510886914SAnson Huang #define IMX8MP_SYS_PLL2_BYPASS 36 4610886914SAnson Huang #define IMX8MP_SYS_PLL3_BYPASS 37 4710886914SAnson Huang #define IMX8MP_AUDIO_PLL1_OUT 38 4810886914SAnson Huang #define IMX8MP_AUDIO_PLL2_OUT 39 4910886914SAnson Huang #define IMX8MP_VIDEO_PLL1_OUT 40 5010886914SAnson Huang #define IMX8MP_DRAM_PLL_OUT 41 5110886914SAnson Huang #define IMX8MP_GPU_PLL_OUT 42 5210886914SAnson Huang #define IMX8MP_VPU_PLL_OUT 43 5310886914SAnson Huang #define IMX8MP_ARM_PLL_OUT 44 5410886914SAnson Huang #define IMX8MP_SYS_PLL1_OUT 45 5510886914SAnson Huang #define IMX8MP_SYS_PLL2_OUT 46 5610886914SAnson Huang #define IMX8MP_SYS_PLL3_OUT 47 5710886914SAnson Huang #define IMX8MP_SYS_PLL1_40M 48 5810886914SAnson Huang #define IMX8MP_SYS_PLL1_80M 49 5910886914SAnson Huang #define IMX8MP_SYS_PLL1_100M 50 6010886914SAnson Huang #define IMX8MP_SYS_PLL1_133M 51 6110886914SAnson Huang #define IMX8MP_SYS_PLL1_160M 52 6210886914SAnson Huang #define IMX8MP_SYS_PLL1_200M 53 6310886914SAnson Huang #define IMX8MP_SYS_PLL1_266M 54 6410886914SAnson Huang #define IMX8MP_SYS_PLL1_400M 55 6510886914SAnson Huang #define IMX8MP_SYS_PLL1_800M 56 6610886914SAnson Huang #define IMX8MP_SYS_PLL2_50M 57 6710886914SAnson Huang #define IMX8MP_SYS_PLL2_100M 58 6810886914SAnson Huang #define IMX8MP_SYS_PLL2_125M 59 6910886914SAnson Huang #define IMX8MP_SYS_PLL2_166M 60 7010886914SAnson Huang #define IMX8MP_SYS_PLL2_200M 61 7110886914SAnson Huang #define IMX8MP_SYS_PLL2_250M 62 7210886914SAnson Huang #define IMX8MP_SYS_PLL2_333M 63 7310886914SAnson Huang #define IMX8MP_SYS_PLL2_500M 64 7410886914SAnson Huang #define IMX8MP_SYS_PLL2_1000M 65 7510886914SAnson Huang #define IMX8MP_CLK_A53_SRC 66 7610886914SAnson Huang #define IMX8MP_CLK_M7_SRC 67 7710886914SAnson Huang #define IMX8MP_CLK_ML_SRC 68 7810886914SAnson Huang #define IMX8MP_CLK_GPU3D_CORE_SRC 69 7910886914SAnson Huang #define IMX8MP_CLK_GPU3D_SHADER_SRC 70 8010886914SAnson Huang #define IMX8MP_CLK_GPU2D_SRC 71 8110886914SAnson Huang #define IMX8MP_CLK_AUDIO_AXI_SRC 72 8210886914SAnson Huang #define IMX8MP_CLK_HSIO_AXI_SRC 73 8310886914SAnson Huang #define IMX8MP_CLK_MEDIA_ISP_SRC 74 8410886914SAnson Huang #define IMX8MP_CLK_A53_CG 75 8510886914SAnson Huang #define IMX8MP_CLK_M4_CG 76 8610886914SAnson Huang #define IMX8MP_CLK_ML_CG 77 8710886914SAnson Huang #define IMX8MP_CLK_GPU3D_CORE_CG 78 8810886914SAnson Huang #define IMX8MP_CLK_GPU3D_SHADER_CG 79 8910886914SAnson Huang #define IMX8MP_CLK_GPU2D_CG 80 9010886914SAnson Huang #define IMX8MP_CLK_AUDIO_AXI_CG 81 9110886914SAnson Huang #define IMX8MP_CLK_HSIO_AXI_CG 82 9210886914SAnson Huang #define IMX8MP_CLK_MEDIA_ISP_CG 83 9310886914SAnson Huang #define IMX8MP_CLK_A53_DIV 84 9410886914SAnson Huang #define IMX8MP_CLK_M7_DIV 85 9510886914SAnson Huang #define IMX8MP_CLK_ML_DIV 86 9610886914SAnson Huang #define IMX8MP_CLK_GPU3D_CORE_DIV 87 9710886914SAnson Huang #define IMX8MP_CLK_GPU3D_SHADER_DIV 88 9810886914SAnson Huang #define IMX8MP_CLK_GPU2D_DIV 89 9910886914SAnson Huang #define IMX8MP_CLK_AUDIO_AXI_DIV 90 10010886914SAnson Huang #define IMX8MP_CLK_HSIO_AXI_DIV 91 10110886914SAnson Huang #define IMX8MP_CLK_MEDIA_ISP_DIV 92 10210886914SAnson Huang #define IMX8MP_CLK_MAIN_AXI 93 10310886914SAnson Huang #define IMX8MP_CLK_ENET_AXI 94 10410886914SAnson Huang #define IMX8MP_CLK_NAND_USDHC_BUS 95 10510886914SAnson Huang #define IMX8MP_CLK_VPU_BUS 96 10610886914SAnson Huang #define IMX8MP_CLK_MEDIA_AXI 97 10710886914SAnson Huang #define IMX8MP_CLK_MEDIA_APB 98 10810886914SAnson Huang #define IMX8MP_CLK_HDMI_APB 99 10910886914SAnson Huang #define IMX8MP_CLK_HDMI_AXI 100 11010886914SAnson Huang #define IMX8MP_CLK_GPU_AXI 101 11110886914SAnson Huang #define IMX8MP_CLK_GPU_AHB 102 11210886914SAnson Huang #define IMX8MP_CLK_NOC 103 11310886914SAnson Huang #define IMX8MP_CLK_NOC_IO 104 11410886914SAnson Huang #define IMX8MP_CLK_ML_AXI 105 11510886914SAnson Huang #define IMX8MP_CLK_ML_AHB 106 11610886914SAnson Huang #define IMX8MP_CLK_AHB 107 11710886914SAnson Huang #define IMX8MP_CLK_AUDIO_AHB 108 11810886914SAnson Huang #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 11910886914SAnson Huang #define IMX8MP_CLK_IPG_ROOT 110 12010886914SAnson Huang #define IMX8MP_CLK_DRAM_ALT 112 12110886914SAnson Huang #define IMX8MP_CLK_DRAM_APB 113 12210886914SAnson Huang #define IMX8MP_CLK_VPU_G1 114 12310886914SAnson Huang #define IMX8MP_CLK_VPU_G2 115 12410886914SAnson Huang #define IMX8MP_CLK_CAN1 116 12510886914SAnson Huang #define IMX8MP_CLK_CAN2 117 12610886914SAnson Huang #define IMX8MP_CLK_MEMREPAIR 118 12710886914SAnson Huang #define IMX8MP_CLK_PCIE_AUX 120 12810886914SAnson Huang #define IMX8MP_CLK_I2C5 121 12910886914SAnson Huang #define IMX8MP_CLK_I2C6 122 13010886914SAnson Huang #define IMX8MP_CLK_SAI1 123 13110886914SAnson Huang #define IMX8MP_CLK_SAI2 124 13210886914SAnson Huang #define IMX8MP_CLK_SAI3 125 13310886914SAnson Huang #define IMX8MP_CLK_SAI4 126 13410886914SAnson Huang #define IMX8MP_CLK_SAI5 127 13510886914SAnson Huang #define IMX8MP_CLK_SAI6 128 13610886914SAnson Huang #define IMX8MP_CLK_ENET_QOS 129 13710886914SAnson Huang #define IMX8MP_CLK_ENET_QOS_TIMER 130 13810886914SAnson Huang #define IMX8MP_CLK_ENET_REF 131 13910886914SAnson Huang #define IMX8MP_CLK_ENET_TIMER 132 14010886914SAnson Huang #define IMX8MP_CLK_ENET_PHY_REF 133 14110886914SAnson Huang #define IMX8MP_CLK_NAND 134 14210886914SAnson Huang #define IMX8MP_CLK_QSPI 135 14310886914SAnson Huang #define IMX8MP_CLK_USDHC1 136 14410886914SAnson Huang #define IMX8MP_CLK_USDHC2 137 14510886914SAnson Huang #define IMX8MP_CLK_I2C1 138 14610886914SAnson Huang #define IMX8MP_CLK_I2C2 139 14710886914SAnson Huang #define IMX8MP_CLK_I2C3 140 14810886914SAnson Huang #define IMX8MP_CLK_I2C4 141 14910886914SAnson Huang #define IMX8MP_CLK_UART1 142 15010886914SAnson Huang #define IMX8MP_CLK_UART2 143 15110886914SAnson Huang #define IMX8MP_CLK_UART3 144 15210886914SAnson Huang #define IMX8MP_CLK_UART4 145 15310886914SAnson Huang #define IMX8MP_CLK_USB_CORE_REF 146 15410886914SAnson Huang #define IMX8MP_CLK_USB_PHY_REF 147 15510886914SAnson Huang #define IMX8MP_CLK_GIC 148 15610886914SAnson Huang #define IMX8MP_CLK_ECSPI1 149 15710886914SAnson Huang #define IMX8MP_CLK_ECSPI2 150 15810886914SAnson Huang #define IMX8MP_CLK_PWM1 151 15910886914SAnson Huang #define IMX8MP_CLK_PWM2 152 16010886914SAnson Huang #define IMX8MP_CLK_PWM3 153 16110886914SAnson Huang #define IMX8MP_CLK_PWM4 154 16210886914SAnson Huang #define IMX8MP_CLK_GPT1 155 16310886914SAnson Huang #define IMX8MP_CLK_GPT2 156 16410886914SAnson Huang #define IMX8MP_CLK_GPT3 157 16510886914SAnson Huang #define IMX8MP_CLK_GPT4 158 16610886914SAnson Huang #define IMX8MP_CLK_GPT5 159 16710886914SAnson Huang #define IMX8MP_CLK_GPT6 160 16810886914SAnson Huang #define IMX8MP_CLK_TRACE 161 16910886914SAnson Huang #define IMX8MP_CLK_WDOG 162 17010886914SAnson Huang #define IMX8MP_CLK_WRCLK 163 17110886914SAnson Huang #define IMX8MP_CLK_IPP_DO_CLKO1 164 17210886914SAnson Huang #define IMX8MP_CLK_IPP_DO_CLKO2 165 17310886914SAnson Huang #define IMX8MP_CLK_HDMI_FDCC_TST 166 174c267bd44SAnson Huang #define IMX8MP_CLK_HDMI_24M 167 17510886914SAnson Huang #define IMX8MP_CLK_HDMI_REF_266M 168 17610886914SAnson Huang #define IMX8MP_CLK_USDHC3 169 17710886914SAnson Huang #define IMX8MP_CLK_MEDIA_CAM1_PIX 170 17810886914SAnson Huang #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 17910886914SAnson Huang #define IMX8MP_CLK_MEDIA_DISP1_PIX 172 18010886914SAnson Huang #define IMX8MP_CLK_MEDIA_CAM2_PIX 173 181afff77ceSJacky Bai #define IMX8MP_CLK_MEDIA_LDB 174 18210886914SAnson Huang #define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 18310886914SAnson Huang #define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 18410886914SAnson Huang #define IMX8MP_CLK_ECSPI3 179 18510886914SAnson Huang #define IMX8MP_CLK_PDM 180 18610886914SAnson Huang #define IMX8MP_CLK_VPU_VC8000E 181 18710886914SAnson Huang #define IMX8MP_CLK_SAI7 182 18810886914SAnson Huang #define IMX8MP_CLK_GPC_ROOT 183 18910886914SAnson Huang #define IMX8MP_CLK_ANAMIX_ROOT 184 19010886914SAnson Huang #define IMX8MP_CLK_CPU_ROOT 185 19110886914SAnson Huang #define IMX8MP_CLK_CSU_ROOT 186 19210886914SAnson Huang #define IMX8MP_CLK_DEBUG_ROOT 187 19310886914SAnson Huang #define IMX8MP_CLK_DRAM1_ROOT 188 19410886914SAnson Huang #define IMX8MP_CLK_ECSPI1_ROOT 189 19510886914SAnson Huang #define IMX8MP_CLK_ECSPI2_ROOT 190 19610886914SAnson Huang #define IMX8MP_CLK_ECSPI3_ROOT 191 19710886914SAnson Huang #define IMX8MP_CLK_ENET1_ROOT 192 19810886914SAnson Huang #define IMX8MP_CLK_GPIO1_ROOT 193 19910886914SAnson Huang #define IMX8MP_CLK_GPIO2_ROOT 194 20010886914SAnson Huang #define IMX8MP_CLK_GPIO3_ROOT 195 20110886914SAnson Huang #define IMX8MP_CLK_GPIO4_ROOT 196 20210886914SAnson Huang #define IMX8MP_CLK_GPIO5_ROOT 197 20310886914SAnson Huang #define IMX8MP_CLK_GPT1_ROOT 198 20410886914SAnson Huang #define IMX8MP_CLK_GPT2_ROOT 199 20510886914SAnson Huang #define IMX8MP_CLK_GPT3_ROOT 200 20610886914SAnson Huang #define IMX8MP_CLK_GPT4_ROOT 201 20710886914SAnson Huang #define IMX8MP_CLK_GPT5_ROOT 202 20810886914SAnson Huang #define IMX8MP_CLK_GPT6_ROOT 203 20910886914SAnson Huang #define IMX8MP_CLK_HS_ROOT 204 21010886914SAnson Huang #define IMX8MP_CLK_I2C1_ROOT 205 21110886914SAnson Huang #define IMX8MP_CLK_I2C2_ROOT 206 21210886914SAnson Huang #define IMX8MP_CLK_I2C3_ROOT 207 21310886914SAnson Huang #define IMX8MP_CLK_I2C4_ROOT 208 21410886914SAnson Huang #define IMX8MP_CLK_IOMUX_ROOT 209 21510886914SAnson Huang #define IMX8MP_CLK_IPMUX1_ROOT 210 21610886914SAnson Huang #define IMX8MP_CLK_IPMUX2_ROOT 211 21710886914SAnson Huang #define IMX8MP_CLK_IPMUX3_ROOT 212 21810886914SAnson Huang #define IMX8MP_CLK_MU_ROOT 213 21910886914SAnson Huang #define IMX8MP_CLK_OCOTP_ROOT 214 22010886914SAnson Huang #define IMX8MP_CLK_OCRAM_ROOT 215 22110886914SAnson Huang #define IMX8MP_CLK_OCRAM_S_ROOT 216 22210886914SAnson Huang #define IMX8MP_CLK_PCIE_ROOT 217 22310886914SAnson Huang #define IMX8MP_CLK_PERFMON1_ROOT 218 22410886914SAnson Huang #define IMX8MP_CLK_PERFMON2_ROOT 219 22510886914SAnson Huang #define IMX8MP_CLK_PWM1_ROOT 220 22610886914SAnson Huang #define IMX8MP_CLK_PWM2_ROOT 221 22710886914SAnson Huang #define IMX8MP_CLK_PWM3_ROOT 222 22810886914SAnson Huang #define IMX8MP_CLK_PWM4_ROOT 223 22910886914SAnson Huang #define IMX8MP_CLK_QOS_ROOT 224 23010886914SAnson Huang #define IMX8MP_CLK_QOS_ENET_ROOT 225 23110886914SAnson Huang #define IMX8MP_CLK_QSPI_ROOT 226 23210886914SAnson Huang #define IMX8MP_CLK_NAND_ROOT 227 23310886914SAnson Huang #define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 23410886914SAnson Huang #define IMX8MP_CLK_RDC_ROOT 229 23510886914SAnson Huang #define IMX8MP_CLK_ROM_ROOT 230 23610886914SAnson Huang #define IMX8MP_CLK_I2C5_ROOT 231 23710886914SAnson Huang #define IMX8MP_CLK_I2C6_ROOT 232 23810886914SAnson Huang #define IMX8MP_CLK_CAN1_ROOT 233 23910886914SAnson Huang #define IMX8MP_CLK_CAN2_ROOT 234 24010886914SAnson Huang #define IMX8MP_CLK_SCTR_ROOT 235 24110886914SAnson Huang #define IMX8MP_CLK_SDMA1_ROOT 236 24210886914SAnson Huang #define IMX8MP_CLK_ENET_QOS_ROOT 237 24310886914SAnson Huang #define IMX8MP_CLK_SEC_DEBUG_ROOT 238 24410886914SAnson Huang #define IMX8MP_CLK_SEMA1_ROOT 239 24510886914SAnson Huang #define IMX8MP_CLK_SEMA2_ROOT 240 24610886914SAnson Huang #define IMX8MP_CLK_IRQ_STEER_ROOT 241 24710886914SAnson Huang #define IMX8MP_CLK_SIM_ENET_ROOT 242 24810886914SAnson Huang #define IMX8MP_CLK_SIM_M_ROOT 243 24910886914SAnson Huang #define IMX8MP_CLK_SIM_MAIN_ROOT 244 25010886914SAnson Huang #define IMX8MP_CLK_SIM_S_ROOT 245 25110886914SAnson Huang #define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 25210886914SAnson Huang #define IMX8MP_CLK_GPU2D_ROOT 247 25310886914SAnson Huang #define IMX8MP_CLK_GPU3D_ROOT 248 25410886914SAnson Huang #define IMX8MP_CLK_SNVS_ROOT 249 25510886914SAnson Huang #define IMX8MP_CLK_TRACE_ROOT 250 25610886914SAnson Huang #define IMX8MP_CLK_UART1_ROOT 251 25710886914SAnson Huang #define IMX8MP_CLK_UART2_ROOT 252 25810886914SAnson Huang #define IMX8MP_CLK_UART3_ROOT 253 25910886914SAnson Huang #define IMX8MP_CLK_UART4_ROOT 254 26010886914SAnson Huang #define IMX8MP_CLK_USB_ROOT 255 26110886914SAnson Huang #define IMX8MP_CLK_USB_PHY_ROOT 256 26210886914SAnson Huang #define IMX8MP_CLK_USDHC1_ROOT 257 26310886914SAnson Huang #define IMX8MP_CLK_USDHC2_ROOT 258 26410886914SAnson Huang #define IMX8MP_CLK_WDOG1_ROOT 259 26510886914SAnson Huang #define IMX8MP_CLK_WDOG2_ROOT 260 26610886914SAnson Huang #define IMX8MP_CLK_WDOG3_ROOT 261 26710886914SAnson Huang #define IMX8MP_CLK_VPU_G1_ROOT 262 26810886914SAnson Huang #define IMX8MP_CLK_GPU_ROOT 263 26910886914SAnson Huang #define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 27010886914SAnson Huang #define IMX8MP_CLK_VPU_VC8KE_ROOT 265 27110886914SAnson Huang #define IMX8MP_CLK_VPU_G2_ROOT 266 27210886914SAnson Huang #define IMX8MP_CLK_NPU_ROOT 267 27310886914SAnson Huang #define IMX8MP_CLK_HSIO_ROOT 268 27410886914SAnson Huang #define IMX8MP_CLK_MEDIA_APB_ROOT 269 27510886914SAnson Huang #define IMX8MP_CLK_MEDIA_AXI_ROOT 270 27610886914SAnson Huang #define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 27710886914SAnson Huang #define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 27810886914SAnson Huang #define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 27910886914SAnson Huang #define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 28010886914SAnson Huang #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 28110886914SAnson Huang #define IMX8MP_CLK_MEDIA_ISP_ROOT 276 28210886914SAnson Huang #define IMX8MP_CLK_USDHC3_ROOT 277 28310886914SAnson Huang #define IMX8MP_CLK_HDMI_ROOT 278 28410886914SAnson Huang #define IMX8MP_CLK_XTAL_ROOT 279 28510886914SAnson Huang #define IMX8MP_CLK_PLL_ROOT 280 28610886914SAnson Huang #define IMX8MP_CLK_TSENSOR_ROOT 281 28710886914SAnson Huang #define IMX8MP_CLK_VPU_ROOT 282 28810886914SAnson Huang #define IMX8MP_CLK_MRPR_ROOT 283 28910886914SAnson Huang #define IMX8MP_CLK_AUDIO_ROOT 284 29010886914SAnson Huang #define IMX8MP_CLK_DRAM_ALT_ROOT 285 29110886914SAnson Huang #define IMX8MP_CLK_DRAM_CORE 286 29210886914SAnson Huang #define IMX8MP_CLK_ARM 287 2937ab22721SPeng Fan #define IMX8MP_CLK_A53_CORE 288 29410886914SAnson Huang 29577f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_40M_CG 289 29677f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_80M_CG 290 29777f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_100M_CG 291 29877f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_133M_CG 292 29977f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_160M_CG 293 30077f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_200M_CG 294 30177f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_266M_CG 295 30277f5d2d9SPeng Fan #define IMX8MP_SYS_PLL1_400M_CG 296 30377f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_50M_CG 297 30477f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_100M_CG 298 30577f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_125M_CG 299 30677f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_166M_CG 300 30777f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_200M_CG 301 30877f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_250M_CG 302 30977f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_333M_CG 303 31077f5d2d9SPeng Fan #define IMX8MP_SYS_PLL2_500M_CG 304 31177f5d2d9SPeng Fan 3128c83a8ffSPeng Fan #define IMX8MP_CLK_M7_CORE 305 3138c83a8ffSPeng Fan #define IMX8MP_CLK_ML_CORE 306 3148c83a8ffSPeng Fan #define IMX8MP_CLK_GPU3D_CORE 307 3158c83a8ffSPeng Fan #define IMX8MP_CLK_GPU3D_SHADER_CORE 308 3168c83a8ffSPeng Fan #define IMX8MP_CLK_GPU2D_CORE 309 3178c83a8ffSPeng Fan #define IMX8MP_CLK_AUDIO_AXI 310 3188c83a8ffSPeng Fan #define IMX8MP_CLK_HSIO_AXI 311 3198c83a8ffSPeng Fan #define IMX8MP_CLK_MEDIA_ISP 312 32039772efdSMarek Vasut #define IMX8MP_CLK_MEDIA_DISP2_PIX 313 32143896f56SLucas Stach #define IMX8MP_CLK_CLKOUT1_SEL 314 32243896f56SLucas Stach #define IMX8MP_CLK_CLKOUT1_DIV 315 32343896f56SLucas Stach #define IMX8MP_CLK_CLKOUT1 316 32443896f56SLucas Stach #define IMX8MP_CLK_CLKOUT2_SEL 317 32543896f56SLucas Stach #define IMX8MP_CLK_CLKOUT2_DIV 318 32643896f56SLucas Stach #define IMX8MP_CLK_CLKOUT2 319 3275c1f7f10SLi Jun #define IMX8MP_CLK_USB_SUSP 320 328*36759c4fSAbel Vesa #define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT 329*36759c4fSAbel Vesa #define IMX8MP_CLK_AUDIO_AXI_ROOT 321 330*36759c4fSAbel Vesa #define IMX8MP_CLK_SAI1_ROOT 322 331*36759c4fSAbel Vesa #define IMX8MP_CLK_SAI2_ROOT 323 332*36759c4fSAbel Vesa #define IMX8MP_CLK_SAI3_ROOT 324 333*36759c4fSAbel Vesa #define IMX8MP_CLK_SAI5_ROOT 325 334*36759c4fSAbel Vesa #define IMX8MP_CLK_SAI6_ROOT 326 335*36759c4fSAbel Vesa #define IMX8MP_CLK_SAI7_ROOT 327 336*36759c4fSAbel Vesa #define IMX8MP_CLK_PDM_ROOT 328 33739772efdSMarek Vasut 338*36759c4fSAbel Vesa #define IMX8MP_CLK_END 329 33910886914SAnson Huang 340849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 341849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 342849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 343849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 344849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 345849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 346849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 347849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 348849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 349849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 350849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 351849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 352849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 353849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 354849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 355849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 356849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 357849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 358849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 359849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 360849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 361849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 362849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 363849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 364849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 365849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 366849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 367849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 368849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 369849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 370849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 371849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 372849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 373849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 374849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 375849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 376849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 377849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 378849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 379849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 380849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 381849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 382849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 383849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 384849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 385849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 386849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 387849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 388849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 389849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 390849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 391849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 392849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 393849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 394849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 395849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 396849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 397849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 398849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 399849af490SAbel Vesa 400849af490SAbel Vesa #define IMX8MP_CLK_AUDIOMIX_END 59 401849af490SAbel Vesa 40210886914SAnson Huang #endif 403