1*1e80936aSAnson Huang /* SPDX-License-Identifier: GPL-2.0 */ 2*1e80936aSAnson Huang /* 3*1e80936aSAnson Huang * Copyright 2018-2019 NXP 4*1e80936aSAnson Huang */ 5*1e80936aSAnson Huang 6*1e80936aSAnson Huang #ifndef __DT_BINDINGS_CLOCK_IMX8MN_H 7*1e80936aSAnson Huang #define __DT_BINDINGS_CLOCK_IMX8MN_H 8*1e80936aSAnson Huang 9*1e80936aSAnson Huang #define IMX8MN_CLK_DUMMY 0 10*1e80936aSAnson Huang #define IMX8MN_CLK_32K 1 11*1e80936aSAnson Huang #define IMX8MN_CLK_24M 2 12*1e80936aSAnson Huang #define IMX8MN_OSC_HDMI_CLK 3 13*1e80936aSAnson Huang #define IMX8MN_CLK_EXT1 4 14*1e80936aSAnson Huang #define IMX8MN_CLK_EXT2 5 15*1e80936aSAnson Huang #define IMX8MN_CLK_EXT3 6 16*1e80936aSAnson Huang #define IMX8MN_CLK_EXT4 7 17*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1_REF_SEL 8 18*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2_REF_SEL 9 19*1e80936aSAnson Huang #define IMX8MN_VIDEO_PLL1_REF_SEL 10 20*1e80936aSAnson Huang #define IMX8MN_DRAM_PLL_REF_SEL 11 21*1e80936aSAnson Huang #define IMX8MN_GPU_PLL_REF_SEL 12 22*1e80936aSAnson Huang #define IMX8MN_VPU_PLL_REF_SEL 13 23*1e80936aSAnson Huang #define IMX8MN_ARM_PLL_REF_SEL 14 24*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_REF_SEL 15 25*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_REF_SEL 16 26*1e80936aSAnson Huang #define IMX8MN_SYS_PLL3_REF_SEL 17 27*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1 18 28*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2 19 29*1e80936aSAnson Huang #define IMX8MN_VIDEO_PLL1 20 30*1e80936aSAnson Huang #define IMX8MN_DRAM_PLL 21 31*1e80936aSAnson Huang #define IMX8MN_GPU_PLL 22 32*1e80936aSAnson Huang #define IMX8MN_VPU_PLL 23 33*1e80936aSAnson Huang #define IMX8MN_ARM_PLL 24 34*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1 25 35*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2 26 36*1e80936aSAnson Huang #define IMX8MN_SYS_PLL3 27 37*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1_BYPASS 28 38*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2_BYPASS 29 39*1e80936aSAnson Huang #define IMX8MN_VIDEO_PLL1_BYPASS 30 40*1e80936aSAnson Huang #define IMX8MN_DRAM_PLL_BYPASS 31 41*1e80936aSAnson Huang #define IMX8MN_GPU_PLL_BYPASS 32 42*1e80936aSAnson Huang #define IMX8MN_VPU_PLL_BYPASS 33 43*1e80936aSAnson Huang #define IMX8MN_ARM_PLL_BYPASS 34 44*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_BYPASS 35 45*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_BYPASS 36 46*1e80936aSAnson Huang #define IMX8MN_SYS_PLL3_BYPASS 37 47*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1_OUT 38 48*1e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2_OUT 39 49*1e80936aSAnson Huang #define IMX8MN_VIDEO_PLL1_OUT 40 50*1e80936aSAnson Huang #define IMX8MN_DRAM_PLL_OUT 41 51*1e80936aSAnson Huang #define IMX8MN_GPU_PLL_OUT 42 52*1e80936aSAnson Huang #define IMX8MN_VPU_PLL_OUT 43 53*1e80936aSAnson Huang #define IMX8MN_ARM_PLL_OUT 44 54*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_OUT 45 55*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_OUT 46 56*1e80936aSAnson Huang #define IMX8MN_SYS_PLL3_OUT 47 57*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_40M 48 58*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_80M 49 59*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_100M 50 60*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_133M 51 61*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_160M 52 62*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_200M 53 63*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_266M 54 64*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_400M 55 65*1e80936aSAnson Huang #define IMX8MN_SYS_PLL1_800M 56 66*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_50M 57 67*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_100M 58 68*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_125M 59 69*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_166M 60 70*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_200M 61 71*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_250M 62 72*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_333M 63 73*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_500M 64 74*1e80936aSAnson Huang #define IMX8MN_SYS_PLL2_1000M 65 75*1e80936aSAnson Huang 76*1e80936aSAnson Huang /* CORE CLOCK ROOT */ 77*1e80936aSAnson Huang #define IMX8MN_CLK_A53_SRC 66 78*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_SRC 67 79*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_SHADER_SRC 68 80*1e80936aSAnson Huang #define IMX8MN_CLK_A53_CG 69 81*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_CG 70 82*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_SHADER_CG 71 83*1e80936aSAnson Huang #define IMX8MN_CLK_A53_DIV 72 84*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_DIV 73 85*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_SHADER_DIV 74 86*1e80936aSAnson Huang 87*1e80936aSAnson Huang /* BUS CLOCK ROOT */ 88*1e80936aSAnson Huang #define IMX8MN_CLK_MAIN_AXI 75 89*1e80936aSAnson Huang #define IMX8MN_CLK_ENET_AXI 76 90*1e80936aSAnson Huang #define IMX8MN_CLK_NAND_USDHC_BUS 77 91*1e80936aSAnson Huang #define IMX8MN_CLK_DISP_AXI 78 92*1e80936aSAnson Huang #define IMX8MN_CLK_DISP_APB 79 93*1e80936aSAnson Huang #define IMX8MN_CLK_USB_BUS 80 94*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_AXI 81 95*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_AHB 82 96*1e80936aSAnson Huang #define IMX8MN_CLK_NOC 83 97*1e80936aSAnson Huang #define IMX8MN_CLK_AHB 84 98*1e80936aSAnson Huang #define IMX8MN_CLK_AUDIO_AHB 85 99*1e80936aSAnson Huang 100*1e80936aSAnson Huang /* IPG CLOCK ROOT */ 101*1e80936aSAnson Huang #define IMX8MN_CLK_IPG_ROOT 86 102*1e80936aSAnson Huang #define IMX8MN_CLK_IPG_AUDIO_ROOT 87 103*1e80936aSAnson Huang 104*1e80936aSAnson Huang /* IP */ 105*1e80936aSAnson Huang #define IMX8MN_CLK_DRAM_CORE 88 106*1e80936aSAnson Huang #define IMX8MN_CLK_DRAM_ALT 89 107*1e80936aSAnson Huang #define IMX8MN_CLK_DRAM_APB 90 108*1e80936aSAnson Huang #define IMX8MN_CLK_DRAM_ALT_ROOT 91 109*1e80936aSAnson Huang #define IMX8MN_CLK_DISP_PIXEL 92 110*1e80936aSAnson Huang #define IMX8MN_CLK_SAI2 93 111*1e80936aSAnson Huang #define IMX8MN_CLK_SAI3 94 112*1e80936aSAnson Huang #define IMX8MN_CLK_SAI5 95 113*1e80936aSAnson Huang #define IMX8MN_CLK_SAI6 96 114*1e80936aSAnson Huang #define IMX8MN_CLK_SPDIF1 97 115*1e80936aSAnson Huang #define IMX8MN_CLK_ENET_REF 98 116*1e80936aSAnson Huang #define IMX8MN_CLK_ENET_TIMER 99 117*1e80936aSAnson Huang #define IMX8MN_CLK_ENET_PHY_REF 100 118*1e80936aSAnson Huang #define IMX8MN_CLK_NAND 101 119*1e80936aSAnson Huang #define IMX8MN_CLK_QSPI 102 120*1e80936aSAnson Huang #define IMX8MN_CLK_USDHC1 103 121*1e80936aSAnson Huang #define IMX8MN_CLK_USDHC2 104 122*1e80936aSAnson Huang #define IMX8MN_CLK_I2C1 105 123*1e80936aSAnson Huang #define IMX8MN_CLK_I2C2 106 124*1e80936aSAnson Huang #define IMX8MN_CLK_I2C3 107 125*1e80936aSAnson Huang #define IMX8MN_CLK_I2C4 118 126*1e80936aSAnson Huang #define IMX8MN_CLK_UART1 119 127*1e80936aSAnson Huang #define IMX8MN_CLK_UART2 110 128*1e80936aSAnson Huang #define IMX8MN_CLK_UART3 111 129*1e80936aSAnson Huang #define IMX8MN_CLK_UART4 112 130*1e80936aSAnson Huang #define IMX8MN_CLK_USB_CORE_REF 113 131*1e80936aSAnson Huang #define IMX8MN_CLK_USB_PHY_REF 114 132*1e80936aSAnson Huang #define IMX8MN_CLK_ECSPI1 115 133*1e80936aSAnson Huang #define IMX8MN_CLK_ECSPI2 116 134*1e80936aSAnson Huang #define IMX8MN_CLK_PWM1 117 135*1e80936aSAnson Huang #define IMX8MN_CLK_PWM2 118 136*1e80936aSAnson Huang #define IMX8MN_CLK_PWM3 119 137*1e80936aSAnson Huang #define IMX8MN_CLK_PWM4 120 138*1e80936aSAnson Huang #define IMX8MN_CLK_WDOG 121 139*1e80936aSAnson Huang #define IMX8MN_CLK_WRCLK 122 140*1e80936aSAnson Huang #define IMX8MN_CLK_CLKO1 123 141*1e80936aSAnson Huang #define IMX8MN_CLK_CLKO2 124 142*1e80936aSAnson Huang #define IMX8MN_CLK_DSI_CORE 125 143*1e80936aSAnson Huang #define IMX8MN_CLK_DSI_PHY_REF 126 144*1e80936aSAnson Huang #define IMX8MN_CLK_DSI_DBI 127 145*1e80936aSAnson Huang #define IMX8MN_CLK_USDHC3 128 146*1e80936aSAnson Huang #define IMX8MN_CLK_CAMERA_PIXEL 129 147*1e80936aSAnson Huang #define IMX8MN_CLK_CSI1_PHY_REF 130 148*1e80936aSAnson Huang #define IMX8MN_CLK_CSI2_PHY_REF 131 149*1e80936aSAnson Huang #define IMX8MN_CLK_CSI2_ESC 132 150*1e80936aSAnson Huang #define IMX8MN_CLK_ECSPI3 133 151*1e80936aSAnson Huang #define IMX8MN_CLK_PDM 134 152*1e80936aSAnson Huang #define IMX8MN_CLK_SAI7 135 153*1e80936aSAnson Huang 154*1e80936aSAnson Huang #define IMX8MN_CLK_ECSPI1_ROOT 136 155*1e80936aSAnson Huang #define IMX8MN_CLK_ECSPI2_ROOT 137 156*1e80936aSAnson Huang #define IMX8MN_CLK_ECSPI3_ROOT 138 157*1e80936aSAnson Huang #define IMX8MN_CLK_ENET1_ROOT 139 158*1e80936aSAnson Huang #define IMX8MN_CLK_GPIO1_ROOT 140 159*1e80936aSAnson Huang #define IMX8MN_CLK_GPIO2_ROOT 141 160*1e80936aSAnson Huang #define IMX8MN_CLK_GPIO3_ROOT 142 161*1e80936aSAnson Huang #define IMX8MN_CLK_GPIO4_ROOT 143 162*1e80936aSAnson Huang #define IMX8MN_CLK_GPIO5_ROOT 144 163*1e80936aSAnson Huang #define IMX8MN_CLK_I2C1_ROOT 145 164*1e80936aSAnson Huang #define IMX8MN_CLK_I2C2_ROOT 146 165*1e80936aSAnson Huang #define IMX8MN_CLK_I2C3_ROOT 147 166*1e80936aSAnson Huang #define IMX8MN_CLK_I2C4_ROOT 148 167*1e80936aSAnson Huang #define IMX8MN_CLK_MU_ROOT 149 168*1e80936aSAnson Huang #define IMX8MN_CLK_OCOTP_ROOT 150 169*1e80936aSAnson Huang #define IMX8MN_CLK_PWM1_ROOT 151 170*1e80936aSAnson Huang #define IMX8MN_CLK_PWM2_ROOT 152 171*1e80936aSAnson Huang #define IMX8MN_CLK_PWM3_ROOT 153 172*1e80936aSAnson Huang #define IMX8MN_CLK_PWM4_ROOT 154 173*1e80936aSAnson Huang #define IMX8MN_CLK_QSPI_ROOT 155 174*1e80936aSAnson Huang #define IMX8MN_CLK_NAND_ROOT 156 175*1e80936aSAnson Huang #define IMX8MN_CLK_SAI2_ROOT 157 176*1e80936aSAnson Huang #define IMX8MN_CLK_SAI2_IPG 158 177*1e80936aSAnson Huang #define IMX8MN_CLK_SAI3_ROOT 159 178*1e80936aSAnson Huang #define IMX8MN_CLK_SAI3_IPG 160 179*1e80936aSAnson Huang #define IMX8MN_CLK_SAI5_ROOT 161 180*1e80936aSAnson Huang #define IMX8MN_CLK_SAI5_IPG 162 181*1e80936aSAnson Huang #define IMX8MN_CLK_SAI6_ROOT 163 182*1e80936aSAnson Huang #define IMX8MN_CLK_SAI6_IPG 164 183*1e80936aSAnson Huang #define IMX8MN_CLK_SAI7_ROOT 165 184*1e80936aSAnson Huang #define IMX8MN_CLK_SAI7_IPG 166 185*1e80936aSAnson Huang #define IMX8MN_CLK_SDMA1_ROOT 167 186*1e80936aSAnson Huang #define IMX8MN_CLK_SDMA2_ROOT 168 187*1e80936aSAnson Huang #define IMX8MN_CLK_UART1_ROOT 169 188*1e80936aSAnson Huang #define IMX8MN_CLK_UART2_ROOT 170 189*1e80936aSAnson Huang #define IMX8MN_CLK_UART3_ROOT 171 190*1e80936aSAnson Huang #define IMX8MN_CLK_UART4_ROOT 172 191*1e80936aSAnson Huang #define IMX8MN_CLK_USB1_CTRL_ROOT 173 192*1e80936aSAnson Huang #define IMX8MN_CLK_USDHC1_ROOT 174 193*1e80936aSAnson Huang #define IMX8MN_CLK_USDHC2_ROOT 175 194*1e80936aSAnson Huang #define IMX8MN_CLK_WDOG1_ROOT 176 195*1e80936aSAnson Huang #define IMX8MN_CLK_WDOG2_ROOT 177 196*1e80936aSAnson Huang #define IMX8MN_CLK_WDOG3_ROOT 178 197*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_BUS_ROOT 179 198*1e80936aSAnson Huang #define IMX8MN_CLK_ASRC_ROOT 180 199*1e80936aSAnson Huang #define IMX8MN_CLK_GPU3D_ROOT 181 200*1e80936aSAnson Huang #define IMX8MN_CLK_PDM_ROOT 182 201*1e80936aSAnson Huang #define IMX8MN_CLK_PDM_IPG 183 202*1e80936aSAnson Huang #define IMX8MN_CLK_DISP_AXI_ROOT 184 203*1e80936aSAnson Huang #define IMX8MN_CLK_DISP_APB_ROOT 185 204*1e80936aSAnson Huang #define IMX8MN_CLK_DISP_PIXEL_ROOT 186 205*1e80936aSAnson Huang #define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 206*1e80936aSAnson Huang #define IMX8MN_CLK_USDHC3_ROOT 188 207*1e80936aSAnson Huang #define IMX8MN_CLK_SDMA3_ROOT 189 208*1e80936aSAnson Huang #define IMX8MN_CLK_TMU_ROOT 190 209*1e80936aSAnson Huang #define IMX8MN_CLK_ARM 191 210*1e80936aSAnson Huang #define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 211*1e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_ROOT 193 212*1e80936aSAnson Huang 213*1e80936aSAnson Huang #define IMX8MN_CLK_END 194 214*1e80936aSAnson Huang 215*1e80936aSAnson Huang #endif 216