xref: /linux/include/dt-bindings/clock/imx8mn-clock.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
11e80936aSAnson Huang /* SPDX-License-Identifier: GPL-2.0 */
21e80936aSAnson Huang /*
31e80936aSAnson Huang  * Copyright 2018-2019 NXP
41e80936aSAnson Huang  */
51e80936aSAnson Huang 
61e80936aSAnson Huang #ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
71e80936aSAnson Huang #define __DT_BINDINGS_CLOCK_IMX8MN_H
81e80936aSAnson Huang 
91e80936aSAnson Huang #define IMX8MN_CLK_DUMMY			0
101e80936aSAnson Huang #define IMX8MN_CLK_32K				1
111e80936aSAnson Huang #define IMX8MN_CLK_24M				2
121e80936aSAnson Huang #define IMX8MN_OSC_HDMI_CLK			3
131e80936aSAnson Huang #define IMX8MN_CLK_EXT1				4
141e80936aSAnson Huang #define IMX8MN_CLK_EXT2				5
151e80936aSAnson Huang #define IMX8MN_CLK_EXT3				6
161e80936aSAnson Huang #define IMX8MN_CLK_EXT4				7
171e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1_REF_SEL		8
181e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2_REF_SEL		9
19*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL_REF_SEL		10
20*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL1_REF_SEL		IMX8MN_VIDEO_PLL_REF_SEL
211e80936aSAnson Huang #define IMX8MN_DRAM_PLL_REF_SEL			11
221e80936aSAnson Huang #define IMX8MN_GPU_PLL_REF_SEL			12
23a429c60bSDario Binacchi #define IMX8MN_M7_ALT_PLL_REF_SEL		13
24a429c60bSDario Binacchi #define IMX8MN_VPU_PLL_REF_SEL			IMX8MN_M7_ALT_PLL_REF_SEL
251e80936aSAnson Huang #define IMX8MN_ARM_PLL_REF_SEL			14
261e80936aSAnson Huang #define IMX8MN_SYS_PLL1_REF_SEL			15
271e80936aSAnson Huang #define IMX8MN_SYS_PLL2_REF_SEL			16
281e80936aSAnson Huang #define IMX8MN_SYS_PLL3_REF_SEL			17
291e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1			18
301e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2			19
31*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL			20
32*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL1			IMX8MN_VIDEO_PLL
331e80936aSAnson Huang #define IMX8MN_DRAM_PLL				21
341e80936aSAnson Huang #define IMX8MN_GPU_PLL				22
35a429c60bSDario Binacchi #define IMX8MN_M7_ALT_PLL			23
36a429c60bSDario Binacchi #define IMX8MN_VPU_PLL				IMX8MN_M7_ALT_PLL
371e80936aSAnson Huang #define IMX8MN_ARM_PLL				24
381e80936aSAnson Huang #define IMX8MN_SYS_PLL1				25
391e80936aSAnson Huang #define IMX8MN_SYS_PLL2				26
401e80936aSAnson Huang #define IMX8MN_SYS_PLL3				27
411e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1_BYPASS		28
421e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2_BYPASS		29
43*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL_BYPASS			30
44*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL1_BYPASS		IMX8MN_VIDEO_PLL_BYPASS
451e80936aSAnson Huang #define IMX8MN_DRAM_PLL_BYPASS			31
461e80936aSAnson Huang #define IMX8MN_GPU_PLL_BYPASS			32
47a429c60bSDario Binacchi #define IMX8MN_M7_ALT_PLL_BYPASS		33
48a429c60bSDario Binacchi #define IMX8MN_VPU_PLL_BYPASS			IMX8MN_M7_ALT_PLL_BYPASS
491e80936aSAnson Huang #define IMX8MN_ARM_PLL_BYPASS			34
501e80936aSAnson Huang #define IMX8MN_SYS_PLL1_BYPASS			35
511e80936aSAnson Huang #define IMX8MN_SYS_PLL2_BYPASS			36
521e80936aSAnson Huang #define IMX8MN_SYS_PLL3_BYPASS			37
531e80936aSAnson Huang #define IMX8MN_AUDIO_PLL1_OUT			38
541e80936aSAnson Huang #define IMX8MN_AUDIO_PLL2_OUT			39
55*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL_OUT			40
56*bedcf9d1SDario Binacchi #define IMX8MN_VIDEO_PLL1_OUT			IMX8MN_VIDEO_PLL_OUT
571e80936aSAnson Huang #define IMX8MN_DRAM_PLL_OUT			41
581e80936aSAnson Huang #define IMX8MN_GPU_PLL_OUT			42
59a429c60bSDario Binacchi #define IMX8MN_M7_ALT_PLL_OUT			43
60a429c60bSDario Binacchi #define IMX8MN_VPU_PLL_OUT			IMX8MN_M7_ALT_PLL_OUT
611e80936aSAnson Huang #define IMX8MN_ARM_PLL_OUT			44
621e80936aSAnson Huang #define IMX8MN_SYS_PLL1_OUT			45
631e80936aSAnson Huang #define IMX8MN_SYS_PLL2_OUT			46
641e80936aSAnson Huang #define IMX8MN_SYS_PLL3_OUT			47
651e80936aSAnson Huang #define IMX8MN_SYS_PLL1_40M			48
661e80936aSAnson Huang #define IMX8MN_SYS_PLL1_80M			49
671e80936aSAnson Huang #define IMX8MN_SYS_PLL1_100M			50
681e80936aSAnson Huang #define IMX8MN_SYS_PLL1_133M			51
691e80936aSAnson Huang #define IMX8MN_SYS_PLL1_160M			52
701e80936aSAnson Huang #define IMX8MN_SYS_PLL1_200M			53
711e80936aSAnson Huang #define IMX8MN_SYS_PLL1_266M			54
721e80936aSAnson Huang #define IMX8MN_SYS_PLL1_400M			55
731e80936aSAnson Huang #define IMX8MN_SYS_PLL1_800M			56
741e80936aSAnson Huang #define IMX8MN_SYS_PLL2_50M			57
751e80936aSAnson Huang #define IMX8MN_SYS_PLL2_100M			58
761e80936aSAnson Huang #define IMX8MN_SYS_PLL2_125M			59
771e80936aSAnson Huang #define IMX8MN_SYS_PLL2_166M			60
781e80936aSAnson Huang #define IMX8MN_SYS_PLL2_200M			61
791e80936aSAnson Huang #define IMX8MN_SYS_PLL2_250M			62
801e80936aSAnson Huang #define IMX8MN_SYS_PLL2_333M			63
811e80936aSAnson Huang #define IMX8MN_SYS_PLL2_500M			64
821e80936aSAnson Huang #define IMX8MN_SYS_PLL2_1000M			65
831e80936aSAnson Huang 
841e80936aSAnson Huang /* CORE CLOCK ROOT */
851e80936aSAnson Huang #define IMX8MN_CLK_A53_SRC			66
861e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_SRC			67
871e80936aSAnson Huang #define IMX8MN_CLK_GPU_SHADER_SRC		68
881e80936aSAnson Huang #define IMX8MN_CLK_A53_CG			69
891e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_CG			70
901e80936aSAnson Huang #define IMX8MN_CLK_GPU_SHADER_CG		71
911e80936aSAnson Huang #define IMX8MN_CLK_A53_DIV			72
921e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_DIV			73
931e80936aSAnson Huang #define IMX8MN_CLK_GPU_SHADER_DIV		74
941e80936aSAnson Huang 
951e80936aSAnson Huang /* BUS CLOCK ROOT */
961e80936aSAnson Huang #define IMX8MN_CLK_MAIN_AXI			75
971e80936aSAnson Huang #define IMX8MN_CLK_ENET_AXI			76
981e80936aSAnson Huang #define IMX8MN_CLK_NAND_USDHC_BUS		77
991e80936aSAnson Huang #define IMX8MN_CLK_DISP_AXI			78
1001e80936aSAnson Huang #define IMX8MN_CLK_DISP_APB			79
1011e80936aSAnson Huang #define IMX8MN_CLK_USB_BUS			80
1021e80936aSAnson Huang #define IMX8MN_CLK_GPU_AXI			81
1031e80936aSAnson Huang #define IMX8MN_CLK_GPU_AHB			82
1041e80936aSAnson Huang #define IMX8MN_CLK_NOC				83
1051e80936aSAnson Huang #define IMX8MN_CLK_AHB				84
1061e80936aSAnson Huang #define IMX8MN_CLK_AUDIO_AHB			85
1071e80936aSAnson Huang 
1081e80936aSAnson Huang /* IPG CLOCK ROOT */
1091e80936aSAnson Huang #define IMX8MN_CLK_IPG_ROOT			86
1101e80936aSAnson Huang #define IMX8MN_CLK_IPG_AUDIO_ROOT		87
1111e80936aSAnson Huang 
1121e80936aSAnson Huang /* IP */
1131e80936aSAnson Huang #define IMX8MN_CLK_DRAM_CORE			88
1141e80936aSAnson Huang #define IMX8MN_CLK_DRAM_ALT			89
1151e80936aSAnson Huang #define IMX8MN_CLK_DRAM_APB			90
1161e80936aSAnson Huang #define IMX8MN_CLK_DRAM_ALT_ROOT		91
1171e80936aSAnson Huang #define IMX8MN_CLK_DISP_PIXEL			92
1181e80936aSAnson Huang #define IMX8MN_CLK_SAI2				93
1191e80936aSAnson Huang #define IMX8MN_CLK_SAI3				94
1201e80936aSAnson Huang #define IMX8MN_CLK_SAI5				95
1211e80936aSAnson Huang #define IMX8MN_CLK_SAI6				96
1221e80936aSAnson Huang #define IMX8MN_CLK_SPDIF1			97
1231e80936aSAnson Huang #define IMX8MN_CLK_ENET_REF			98
1241e80936aSAnson Huang #define IMX8MN_CLK_ENET_TIMER			99
1251e80936aSAnson Huang #define IMX8MN_CLK_ENET_PHY_REF			100
1261e80936aSAnson Huang #define IMX8MN_CLK_NAND				101
1271e80936aSAnson Huang #define IMX8MN_CLK_QSPI				102
1281e80936aSAnson Huang #define IMX8MN_CLK_USDHC1			103
1291e80936aSAnson Huang #define IMX8MN_CLK_USDHC2			104
1301e80936aSAnson Huang #define IMX8MN_CLK_I2C1				105
1311e80936aSAnson Huang #define IMX8MN_CLK_I2C2				106
1321e80936aSAnson Huang #define IMX8MN_CLK_I2C3				107
1335eb40257SAnson Huang #define IMX8MN_CLK_I2C4				108
1345eb40257SAnson Huang #define IMX8MN_CLK_UART1			109
1351e80936aSAnson Huang #define IMX8MN_CLK_UART2			110
1361e80936aSAnson Huang #define IMX8MN_CLK_UART3			111
1371e80936aSAnson Huang #define IMX8MN_CLK_UART4			112
1381e80936aSAnson Huang #define IMX8MN_CLK_USB_CORE_REF			113
1391e80936aSAnson Huang #define IMX8MN_CLK_USB_PHY_REF			114
1401e80936aSAnson Huang #define IMX8MN_CLK_ECSPI1			115
1411e80936aSAnson Huang #define IMX8MN_CLK_ECSPI2			116
1421e80936aSAnson Huang #define IMX8MN_CLK_PWM1				117
1431e80936aSAnson Huang #define IMX8MN_CLK_PWM2				118
1441e80936aSAnson Huang #define IMX8MN_CLK_PWM3				119
1451e80936aSAnson Huang #define IMX8MN_CLK_PWM4				120
1461e80936aSAnson Huang #define IMX8MN_CLK_WDOG				121
1471e80936aSAnson Huang #define IMX8MN_CLK_WRCLK			122
1481e80936aSAnson Huang #define IMX8MN_CLK_CLKO1			123
1491e80936aSAnson Huang #define IMX8MN_CLK_CLKO2			124
1501e80936aSAnson Huang #define IMX8MN_CLK_DSI_CORE			125
1511e80936aSAnson Huang #define IMX8MN_CLK_DSI_PHY_REF			126
1521e80936aSAnson Huang #define IMX8MN_CLK_DSI_DBI			127
1531e80936aSAnson Huang #define IMX8MN_CLK_USDHC3			128
1541e80936aSAnson Huang #define IMX8MN_CLK_CAMERA_PIXEL			129
1551e80936aSAnson Huang #define IMX8MN_CLK_CSI1_PHY_REF			130
1561e80936aSAnson Huang #define IMX8MN_CLK_CSI2_PHY_REF			131
1571e80936aSAnson Huang #define IMX8MN_CLK_CSI2_ESC			132
1581e80936aSAnson Huang #define IMX8MN_CLK_ECSPI3			133
1591e80936aSAnson Huang #define IMX8MN_CLK_PDM				134
1601e80936aSAnson Huang #define IMX8MN_CLK_SAI7				135
1611e80936aSAnson Huang 
1621e80936aSAnson Huang #define IMX8MN_CLK_ECSPI1_ROOT			136
1631e80936aSAnson Huang #define IMX8MN_CLK_ECSPI2_ROOT			137
1641e80936aSAnson Huang #define IMX8MN_CLK_ECSPI3_ROOT			138
1651e80936aSAnson Huang #define IMX8MN_CLK_ENET1_ROOT			139
1661e80936aSAnson Huang #define IMX8MN_CLK_GPIO1_ROOT			140
1671e80936aSAnson Huang #define IMX8MN_CLK_GPIO2_ROOT			141
1681e80936aSAnson Huang #define IMX8MN_CLK_GPIO3_ROOT			142
1691e80936aSAnson Huang #define IMX8MN_CLK_GPIO4_ROOT			143
1701e80936aSAnson Huang #define IMX8MN_CLK_GPIO5_ROOT			144
1711e80936aSAnson Huang #define IMX8MN_CLK_I2C1_ROOT			145
1721e80936aSAnson Huang #define IMX8MN_CLK_I2C2_ROOT			146
1731e80936aSAnson Huang #define IMX8MN_CLK_I2C3_ROOT			147
1741e80936aSAnson Huang #define IMX8MN_CLK_I2C4_ROOT			148
1751e80936aSAnson Huang #define IMX8MN_CLK_MU_ROOT			149
1761e80936aSAnson Huang #define IMX8MN_CLK_OCOTP_ROOT			150
1771e80936aSAnson Huang #define IMX8MN_CLK_PWM1_ROOT			151
1781e80936aSAnson Huang #define IMX8MN_CLK_PWM2_ROOT			152
1791e80936aSAnson Huang #define IMX8MN_CLK_PWM3_ROOT			153
1801e80936aSAnson Huang #define IMX8MN_CLK_PWM4_ROOT			154
1811e80936aSAnson Huang #define IMX8MN_CLK_QSPI_ROOT			155
1821e80936aSAnson Huang #define IMX8MN_CLK_NAND_ROOT			156
1831e80936aSAnson Huang #define IMX8MN_CLK_SAI2_ROOT			157
1841e80936aSAnson Huang #define IMX8MN_CLK_SAI2_IPG			158
1851e80936aSAnson Huang #define IMX8MN_CLK_SAI3_ROOT			159
1861e80936aSAnson Huang #define IMX8MN_CLK_SAI3_IPG			160
1871e80936aSAnson Huang #define IMX8MN_CLK_SAI5_ROOT			161
1881e80936aSAnson Huang #define IMX8MN_CLK_SAI5_IPG			162
1891e80936aSAnson Huang #define IMX8MN_CLK_SAI6_ROOT			163
1901e80936aSAnson Huang #define IMX8MN_CLK_SAI6_IPG			164
1911e80936aSAnson Huang #define IMX8MN_CLK_SAI7_ROOT			165
1921e80936aSAnson Huang #define IMX8MN_CLK_SAI7_IPG			166
1931e80936aSAnson Huang #define IMX8MN_CLK_SDMA1_ROOT			167
1941e80936aSAnson Huang #define IMX8MN_CLK_SDMA2_ROOT			168
1951e80936aSAnson Huang #define IMX8MN_CLK_UART1_ROOT			169
1961e80936aSAnson Huang #define IMX8MN_CLK_UART2_ROOT			170
1971e80936aSAnson Huang #define IMX8MN_CLK_UART3_ROOT			171
1981e80936aSAnson Huang #define IMX8MN_CLK_UART4_ROOT			172
1991e80936aSAnson Huang #define IMX8MN_CLK_USB1_CTRL_ROOT		173
2001e80936aSAnson Huang #define IMX8MN_CLK_USDHC1_ROOT			174
2011e80936aSAnson Huang #define IMX8MN_CLK_USDHC2_ROOT			175
2021e80936aSAnson Huang #define IMX8MN_CLK_WDOG1_ROOT			176
2031e80936aSAnson Huang #define IMX8MN_CLK_WDOG2_ROOT			177
2041e80936aSAnson Huang #define IMX8MN_CLK_WDOG3_ROOT			178
2051e80936aSAnson Huang #define IMX8MN_CLK_GPU_BUS_ROOT			179
2061e80936aSAnson Huang #define IMX8MN_CLK_ASRC_ROOT			180
2071e80936aSAnson Huang #define IMX8MN_CLK_GPU3D_ROOT			181
2081e80936aSAnson Huang #define IMX8MN_CLK_PDM_ROOT			182
2091e80936aSAnson Huang #define IMX8MN_CLK_PDM_IPG			183
2101e80936aSAnson Huang #define IMX8MN_CLK_DISP_AXI_ROOT		184
2111e80936aSAnson Huang #define IMX8MN_CLK_DISP_APB_ROOT		185
2121e80936aSAnson Huang #define IMX8MN_CLK_DISP_PIXEL_ROOT		186
2131e80936aSAnson Huang #define IMX8MN_CLK_CAMERA_PIXEL_ROOT		187
2141e80936aSAnson Huang #define IMX8MN_CLK_USDHC3_ROOT			188
2151e80936aSAnson Huang #define IMX8MN_CLK_SDMA3_ROOT			189
2161e80936aSAnson Huang #define IMX8MN_CLK_TMU_ROOT			190
2171e80936aSAnson Huang #define IMX8MN_CLK_ARM				191
2181e80936aSAnson Huang #define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK	192
2191e80936aSAnson Huang #define IMX8MN_CLK_GPU_CORE_ROOT		193
220be378b60SLeonard Crestez #define IMX8MN_CLK_GIC				194
2211e80936aSAnson Huang 
222e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_40M_CG			195
223e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_80M_CG			196
224e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_100M_CG			197
225e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_133M_CG			198
226e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_160M_CG			199
227e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_200M_CG			200
228e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_266M_CG			201
229e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL1_400M_CG			202
230e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_50M_CG			203
231e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_100M_CG			204
232e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_125M_CG			205
233e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_166M_CG			206
234e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_200M_CG			207
235e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_250M_CG			208
236e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_333M_CG			209
237e8688fe8SLeonard Crestez #define IMX8MN_SYS_PLL2_500M_CG			210
238e8688fe8SLeonard Crestez 
239d2d46dfaSHoria Geantă #define IMX8MN_CLK_SNVS_ROOT			211
24033db2ce7SPeng Fan #define IMX8MN_CLK_GPU_CORE			212
24133db2ce7SPeng Fan #define IMX8MN_CLK_GPU_SHADER			213
242d2d46dfaSHoria Geantă 
243c69def88SPeng Fan #define IMX8MN_CLK_A53_CORE			214
244c69def88SPeng Fan 
2453af4df65SLucas Stach #define IMX8MN_CLK_CLKOUT1_SEL			215
2463af4df65SLucas Stach #define IMX8MN_CLK_CLKOUT1_DIV			216
2473af4df65SLucas Stach #define IMX8MN_CLK_CLKOUT1			217
2483af4df65SLucas Stach #define IMX8MN_CLK_CLKOUT2_SEL			218
2493af4df65SLucas Stach #define IMX8MN_CLK_CLKOUT2_DIV			219
2503af4df65SLucas Stach #define IMX8MN_CLK_CLKOUT2			220
2513af4df65SLucas Stach 
25286842d25SMarek Vasut #define IMX8MN_CLK_M7_CORE			221
25386842d25SMarek Vasut 
2549b305019SAlvin Šipraga #define IMX8MN_CLK_GPT_3M			222
2559b305019SAlvin Šipraga #define IMX8MN_CLK_GPT1				223
2569b305019SAlvin Šipraga #define IMX8MN_CLK_GPT1_ROOT			224
2579b305019SAlvin Šipraga #define IMX8MN_CLK_GPT2				225
2589b305019SAlvin Šipraga #define IMX8MN_CLK_GPT2_ROOT			226
2599b305019SAlvin Šipraga #define IMX8MN_CLK_GPT3				227
2609b305019SAlvin Šipraga #define IMX8MN_CLK_GPT3_ROOT			228
2619b305019SAlvin Šipraga #define IMX8MN_CLK_GPT4				229
2629b305019SAlvin Šipraga #define IMX8MN_CLK_GPT4_ROOT			230
2639b305019SAlvin Šipraga #define IMX8MN_CLK_GPT5				231
2649b305019SAlvin Šipraga #define IMX8MN_CLK_GPT5_ROOT			232
2659b305019SAlvin Šipraga #define IMX8MN_CLK_GPT6				233
2669b305019SAlvin Šipraga #define IMX8MN_CLK_GPT6_ROOT			234
2679b305019SAlvin Šipraga 
2689b305019SAlvin Šipraga #define IMX8MN_CLK_END				235
2691e80936aSAnson Huang 
2701e80936aSAnson Huang #endif
271