1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ac36187bSAlexander Shiyan /* 3ac36187bSAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4ac36187bSAlexander Shiyan */ 5ac36187bSAlexander Shiyan 6ac36187bSAlexander Shiyan #ifndef __DT_BINDINGS_CLOCK_IMX1_H 7ac36187bSAlexander Shiyan #define __DT_BINDINGS_CLOCK_IMX1_H 8ac36187bSAlexander Shiyan 9ac36187bSAlexander Shiyan #define IMX1_CLK_DUMMY 0 10ac36187bSAlexander Shiyan #define IMX1_CLK_CLK32 1 11ac36187bSAlexander Shiyan #define IMX1_CLK_CLK16M_EXT 2 12ac36187bSAlexander Shiyan #define IMX1_CLK_CLK16M 3 13ac36187bSAlexander Shiyan #define IMX1_CLK_CLK32_PREMULT 4 14ac36187bSAlexander Shiyan #define IMX1_CLK_PREM 5 15ac36187bSAlexander Shiyan #define IMX1_CLK_MPLL 6 16ac36187bSAlexander Shiyan #define IMX1_CLK_MPLL_GATE 7 17ac36187bSAlexander Shiyan #define IMX1_CLK_SPLL 8 18ac36187bSAlexander Shiyan #define IMX1_CLK_SPLL_GATE 9 19ac36187bSAlexander Shiyan #define IMX1_CLK_MCU 10 20ac36187bSAlexander Shiyan #define IMX1_CLK_FCLK 11 21ac36187bSAlexander Shiyan #define IMX1_CLK_HCLK 12 22ac36187bSAlexander Shiyan #define IMX1_CLK_CLK48M 13 23ac36187bSAlexander Shiyan #define IMX1_CLK_PER1 14 24ac36187bSAlexander Shiyan #define IMX1_CLK_PER2 15 25ac36187bSAlexander Shiyan #define IMX1_CLK_PER3 16 26ac36187bSAlexander Shiyan #define IMX1_CLK_CLKO 17 27ac36187bSAlexander Shiyan #define IMX1_CLK_UART3_GATE 18 28ac36187bSAlexander Shiyan #define IMX1_CLK_SSI2_GATE 19 29ac36187bSAlexander Shiyan #define IMX1_CLK_BROM_GATE 20 30ac36187bSAlexander Shiyan #define IMX1_CLK_DMA_GATE 21 31ac36187bSAlexander Shiyan #define IMX1_CLK_CSI_GATE 22 32ac36187bSAlexander Shiyan #define IMX1_CLK_MMA_GATE 23 33ac36187bSAlexander Shiyan #define IMX1_CLK_USBD_GATE 24 34ac36187bSAlexander Shiyan #define IMX1_CLK_MAX 25 35ac36187bSAlexander Shiyan 36ac36187bSAlexander Shiyan #endif 37