1*ac36187bSAlexander Shiyan /* 2*ac36187bSAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 3*ac36187bSAlexander Shiyan * 4*ac36187bSAlexander Shiyan * This program is free software; you can redistribute it and/or modify 5*ac36187bSAlexander Shiyan * it under the terms of the GNU General Public License version 2 as 6*ac36187bSAlexander Shiyan * published by the Free Software Foundation. 7*ac36187bSAlexander Shiyan * 8*ac36187bSAlexander Shiyan */ 9*ac36187bSAlexander Shiyan 10*ac36187bSAlexander Shiyan #ifndef __DT_BINDINGS_CLOCK_IMX1_H 11*ac36187bSAlexander Shiyan #define __DT_BINDINGS_CLOCK_IMX1_H 12*ac36187bSAlexander Shiyan 13*ac36187bSAlexander Shiyan #define IMX1_CLK_DUMMY 0 14*ac36187bSAlexander Shiyan #define IMX1_CLK_CLK32 1 15*ac36187bSAlexander Shiyan #define IMX1_CLK_CLK16M_EXT 2 16*ac36187bSAlexander Shiyan #define IMX1_CLK_CLK16M 3 17*ac36187bSAlexander Shiyan #define IMX1_CLK_CLK32_PREMULT 4 18*ac36187bSAlexander Shiyan #define IMX1_CLK_PREM 5 19*ac36187bSAlexander Shiyan #define IMX1_CLK_MPLL 6 20*ac36187bSAlexander Shiyan #define IMX1_CLK_MPLL_GATE 7 21*ac36187bSAlexander Shiyan #define IMX1_CLK_SPLL 8 22*ac36187bSAlexander Shiyan #define IMX1_CLK_SPLL_GATE 9 23*ac36187bSAlexander Shiyan #define IMX1_CLK_MCU 10 24*ac36187bSAlexander Shiyan #define IMX1_CLK_FCLK 11 25*ac36187bSAlexander Shiyan #define IMX1_CLK_HCLK 12 26*ac36187bSAlexander Shiyan #define IMX1_CLK_CLK48M 13 27*ac36187bSAlexander Shiyan #define IMX1_CLK_PER1 14 28*ac36187bSAlexander Shiyan #define IMX1_CLK_PER2 15 29*ac36187bSAlexander Shiyan #define IMX1_CLK_PER3 16 30*ac36187bSAlexander Shiyan #define IMX1_CLK_CLKO 17 31*ac36187bSAlexander Shiyan #define IMX1_CLK_UART3_GATE 18 32*ac36187bSAlexander Shiyan #define IMX1_CLK_SSI2_GATE 19 33*ac36187bSAlexander Shiyan #define IMX1_CLK_BROM_GATE 20 34*ac36187bSAlexander Shiyan #define IMX1_CLK_DMA_GATE 21 35*ac36187bSAlexander Shiyan #define IMX1_CLK_CSI_GATE 22 36*ac36187bSAlexander Shiyan #define IMX1_CLK_MMA_GATE 23 37*ac36187bSAlexander Shiyan #define IMX1_CLK_USBD_GATE 24 38*ac36187bSAlexander Shiyan #define IMX1_CLK_MAX 25 39*ac36187bSAlexander Shiyan 40*ac36187bSAlexander Shiyan #endif 41